參數(shù)資料
型號: M58CR064-ZBT
廠商: 意法半導體
英文描述: 64 Mbit 4Mb x 16, Dual Bank, Burst 1.8V Supply Flash Memory
中文描述: 64兆位4Mb的× 16,雙行,突發(fā)1.8V電源快閃記憶體
文件頁數(shù): 69/70頁
文件大小: 1000K
代理商: M58CR064-ZBT
69/70
M58CR064C, M58CR064D, M58CR064P, M58CR064Q
24-Feb-2003
9.2
Revision History moved to end of document.
90ns Speed Class added. Bank Erase Command moved to Factory Program
Commands section. Bank Erase cycles limited to 100 per Block.
WAIT signal modified in Figure 7, Wait Configuration Example. WAIT behavior
modified. Burst sequence in wrapped configuration and Burst sequence start
specified in Synchronous Burst Read Mode paragraph. Erase replaced by Block
Erase in Tables 11 and 12, Dual Operations allowed in Other Bank and in Same
Bank, respectively. Latch signal corrected in Figure 11, Asynchronous Page Read
AC Waveforms. Daisy Chain added.
06-Jun-2003
9.3
V
DD
and V
DDQ
minimum values changed for 90ns speed class in Table 16, Operating
and AC Measurement Conditions. Minor text changes.
Date
Version
Revision Details
相關PDF資料
PDF描述
M58CR064C10ZB6T 64 Mbit 4Mb x 16, Dual Bank, Burst 1.8V Supply Flash Memory
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