參數(shù)資料
型號(hào): M58BW016BB80ZA6T
廠商: 意法半導(dǎo)體
英文描述: ER 8C 8#12 SKT PLUG
中文描述: 16兆位512KB的X32號(hào),引導(dǎo)塊,突發(fā)3V電源閃存
文件頁(yè)數(shù): 20/63頁(yè)
文件大小: 895K
代理商: M58BW016BB80ZA6T
M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB
20/63
Table 7. Burst Configuration Register
Note: 1. 4 - 2 - 2 - 2 is not allowed.
2. X latencies can be calculated as: (t
AVQV
– t
LLKH
+ t
QVKH
) + t
SYSTEM MARGIN
< (X -1) t
K.
(X
is an integer number from 4 to 8 and t
K
is the clock period).
3. Y latencies can be calculated as: t
KHQV
+ t
SYSTEM MARGIN
+ t
QVKH
< Y t
K.
4. t
SYSTEM MARGIN
is the time margin required for the calculation.
Bit
Description
Value
Description
M15
Read Select
0
Synchronous Burst Read
1
Asynchronous Read (Default at power-on)
M14
Reserved
M13-M11
X-Latency
(2)
001
Reserved
010
4, 4-1-1-1
(1)
011
5, 5-1-1-1, 5-2-2-2
100
6, 6-1-1-1, 6-2-2-2
101
7, 7-1-1-1, 7-2-2-2
110
8, 8-1-1-1, 8-2-2-2
M10
Reserved
M9
Y-Latency
(3)
0
One Burst Clock cycle
1
Two Burst Clock cycles
M8
Valid Data Ready
0
R valid Low during valid Burst Clock edge
1
R valid Low one data cycle before valid Burst Clock edge
M7
Burst Type
0
Interleaved
1
Sequential
M6
Valid Clock Edge
0
Falling Burst Clock edge
1
Rising Burst Clock edge
M5-M4
Reserved
M3
Wrapping
0
Wrap
1
No wrap
M2-M0
Burst Length
001
4 Double-Words
010
8 Double-Words
111
Continuous
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