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參數(shù)資料
| 型號： | M54HC40102 |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | 通用總線功能 |
| 英文描述： | 8 STAGE PRESETTABLE SYNCHRONOUS DOWN COUNTERS |
| 中文描述： | 8階段預(yù)置同步向下計(jì)數(shù)器 |
| 文件頁數(shù)： | 1/14頁 |
| 文件大小： | 300K |
| 代理商： | M54HC40102 |
M54/74HC40102
M54/74HC40103
March 1993
8 STAGE PRESETTABLE SYNCHRONOUS DOWN COUNTERS
.
HIGH SPEED
f
MAX
= 40 MHz (TYP.) at V
CC
= 5 V
.
LOWPOWER DISSIPATION
I
CC
= 4
μ
A(MAX.) at T
A
= 25
°
C
.
HIGH NOISE IMMUNITY
V
NIH
= V
NIL
= 28 % V
CC
(MIN.)
.
OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
.
SYMMETRICAL OUTPUT IMPEDANCE
|I
OH
| = I
OL
= 4 mA (MIN.)
.
BALANCEDPROPAGATION DELAYS
t
PLH
= t
PHL
.
WIDE OPERATING VOLTAGE RANGE
V
CC
(OPR) = 2 V to 6 V
.
PIN AND FUNCTION COMPATIBLE WITH
40102B/40103B
B1R
(Plastic Package)
ORDER CODES :
M54HCXXXXXF1R
M74HCXXXXXB1R
M74HCXXXXXM1R
M74HCXXXXX C1R
F1R
(CeramicPackage)
M1R
(MicroPackage)
C1R
(Chip Carrier)
PIN CONNECTIONS
(top view)
NC =
No Internal
Connection
DESCRIPTION
The M54/74HC40102/40103 are highspeed CMOS
8-STAGE
PRESETTABLE
DOWN COUNTERS fabricated with silicon gate
C
2
MOS technology. They achieve the high speed
operation similar to equivalent LSTTL while main-
tainingthe CMOS lowpower dissipation.
The HC40102, and HC40103 consist of an 8-stage
synchronous down counter with a single output
which is active when the internal count is zero. The
HC40102 is configured as two cascaded 4-bit BCD
counters, and the HC40103 contains a single 8-bit
binarycounter. Each type hascontrol inputs for en-
ablingordisabling the clock,for clearing thecounter
to itsmaximum count, and forpresetting thecounter
eithersynchronously or asynchronously. All control
inputs and the CARRY-OUT/ZERO-DETECT out-
put are active-low logic. In normal operation, the
counter is decremented by one count on eachposi-
tive transition of the CLOCK. Counting is inhibited
when the CARRY-IN/COUNTER ENABLE (CI/CE)
input is high. The CARRY-OUT/ZERO-DETECT
(CO/ZD) output goes low when the count reaches
zero if the CI/CE input is low, and remains low for
one full clock period. When the SYNCHRONOUS
PRESET-ENABLE (SPE) input is low, data at the J
input is clocked into the counteron the next positive
clocktransition regardless of thestate of the CI/CE
input.
SYNCHRONOUS
1/14
相關(guān)PDF資料 |
PDF描述 |
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| M54HC40102B1R | 8 STAGE PRESETTABLE SYNCHRONOUS DOWN COUNTERS |
| M54HC40102C1R | 8 STAGE PRESETTABLE SYNCHRONOUS DOWN COUNTERS |
| M54HC40102F1R | 8 STAGE PRESETTABLE SYNCHRONOUS DOWN COUNTERS |
| M54HC40102M1R | 8 STAGE PRESETTABLE SYNCHRONOUS DOWN COUNTERS |
| M54HC4011F1R | BCD TO 7 SEGMENT LATCH/DECODER DRIVER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M54HC40102B1R | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8 STAGE PRESETTABLE SYNCHRONOUS DOWN COUNTERS |
| M54HC40102C1R | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8 STAGE PRESETTABLE SYNCHRONOUS DOWN COUNTERS |
| M54HC40102F1R | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8 STAGE PRESETTABLE SYNCHRONOUS DOWN COUNTERS |
| M54HC40102M1R | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8 STAGE PRESETTABLE SYNCHRONOUS DOWN COUNTERS |
| M54HC40103 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8 STAGE PRESETTABLE SYNCHRONOUS DOWN COUNTERS |
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