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參數(shù)資料
| 型號(hào)： | M48Z02-200PC6TR |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 5V, 16 Kbit (2Kb x 8) ZEROPOWER SRAM |
| 中文描述： | 5V的，16千位（2KB的× 8）ZEROPOWER的SRAM |
| 文件頁數(shù)： | 3/12頁 |
| 文件大小： | 85K |
| 代理商： | M48Z02-200PC6TR |
AI01019
5V
OUT
CL = 100pF
CL includes JIG capacitance
1.8k
DEVICE
UNDER
TEST
1k
Figure 4. AC Testing Load Circuit
Input Rise and Fall Times
≤
5ns
Input Pulse Voltages
0V to 3V
Input and Output Timing Ref. Voltages
1.5V
Note that Output Hi-Z is defined as the point where data is no
longer driven.
Table 4. AC Measurement Conditions
AI01255
LITHIUM
CELL
VPFD
VCC
VSS
VOLTAGE SENSE
AND
SWITCHING
CIRCUITRY
2K x 8
SRAM ARRAY
A0-A10
DQ0-DQ7
E
W
G
POWER
Figure 3. Block Diagram
READ MODE
The M48Z02/12 is in the Read Mode whenever W
(Write Enable) is high and E (Chip Enable) is low.
The device architecture allows ripple-through ac-
cess of data from eight of 16,384 locations in the
static storage array. Thus, the unique address
specified by the 11 Address Inputs defines which
one of the 2,048 bytes of data is to be accessed.
Valid data will be available at the Data I/O pins
within Address Access time (t
AVQV
) after the last
address input signal is stable, providing that the E
and G access times are also satisfied. If the E and
G access times are not met, valid data will be
available after the latter of the Chip Enable Access
time (t
ELQV
) or Output Enable Access time (t
GLQV
).
The state of the eight three-state Data I/O signals
is controlled by E and G. If the outputs are activated
before t
AVQV
, the data lines will be driven to an
indeterminate state until t
AVQV
. If the Address In-
puts are changed while E and G remain active,
output data will remain valid for Output Data Hold
time (t
AXQX
) but will go indeterminate until the next
Address Access.
3/12
M48Z02, M48Z12
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| M48Z02-70PC6TR | FILTER, FRONT END SAW, 868.30MHZ; Attenuation, 1 GHz:40dB; Attenuation, 10 MHz:55dB; Attenuation, 20 MHz:55dB; Bandwidth:.78MHz; Case style:QCC8C; Depth, external:5.0mm; Frequency, min:868.30Hz; Height:1.35mm; Insertion loss:2.7dB; RoHS Compliant: Yes |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M48Z02-70PC1 | 功能描述:NVRAM 16K (2Kx8) 70ns RoHS:否 制造商:Maxim Integrated 數(shù)據(jù)總線寬度:8 bit 存儲(chǔ)容量:1024 Kbit 組織:128 K x 8 接口類型:Parallel 訪問時(shí)間:70 ns 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 工作電流:85 mA 最大工作溫度:+ 70 C 最小工作溫度:0 C 封裝 / 箱體:EDIP 封裝:Tube |
| M48Z02-70PC1 | 制造商:STMicroelectronics 功能描述:IC NVRAM 10 YR BATTERY 16K 48Z02 |
| M48Z02-70PC1TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5V, 16 Kbit (2Kb x 8) ZEROPOWER SRAM |
| M48Z02-70PC6 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5V, 16 Kbit (2Kb x 8) ZEROPOWER SRAM |
| M48Z02-70PC6TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5V, 16 Kbit (2Kb x 8) ZEROPOWER SRAM |
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