參數(shù)資料
型號(hào)： M48TY-85PM1
廠商： 意法半導(dǎo)體
元件分類： SRAM
英文描述： 3.3V-5V 1 Mbit 128Kb x8 TIMEKEEPER SRAM
中文描述： 3.3 - 5V的1兆位的SRAM 128KB的x8計(jì)時(shí)器
文件頁(yè)數(shù)： 14/33頁(yè)
文件大?。?/td> 477K
代理商： M48TY-85PM1
M48T201Y, M48T201V
14/33
CLOCK OPERATION
TIMEKEEPER
Registers
The M48T201Y/V offers 16 internal registers
which contain TIMEKEEPER
, Alarm, Watchdog,
Flag, and Control data (see
Table 5., page 15
).
These registers are memory locations which con-
tain external (user accessible) and internal copies
of the data (usually referred to as BiPORT
TIMEKEEPER cells). The external copies are in-
dependent of internal functions except that they
are updated periodically by the simultaneous
transfer of the incremented internal copy. TIME-
KEEPER and Alarm Registers store data in BCD.
Control, Watchdog and Flags (Bits D0 to D3) Reg-
isters store data in Binary Format.
Reading the Clock
Updates to the TIMEKEEPER registers should be
halted before clock data is read to prevent reading
data in transition. The BiPORT TIMEKEEPER
cells in the RAM array are only data registers and
not the actual clock counters, so updating the reg-
isters can be halted without disturbing the clock it-
self.
Updating is halted when a '1' is written to the
READ Bit, D6 in the Control Register (7FFF8h). As
long as a '1' remains in that position, updating is
halted. After a halt is issued, the registers reflect
the count; that is, the day, date, and time that were
current at the moment the halt command was is-
sued.
All of the TIMEKEEPER registers are updated si-
multaneously. A halt will not interrupt an update in
progress. Updating occurs approximately 1 sec-
ond after the READ Bit is reset to a '0.'
Setting the Clock
Bit D7 of the Control Register (7FFF8h) is the
WRITE Bit. Setting the WRITE Bit to a '1,' like the
READ Bit, halts updates to the TIMEKEEPER reg-
isters. The user can then load them with the cor-
rect day, date, and time data in 24-hour BCD
format (see
Table 5., page 15
).
Resetting the WRITE Bit to a '0' then transfers the
values of all time registers (7FFFFh-7FFF9h,
7FFF1h) to the actual TIMEKEEPER counters and
allows normal operation to resume. After the
WRITE Bit is reset, the next clock update will occur
approximately one second later.
Note:
Upon power-up following a power failure,
both the WRITE Bit and the READ Bit will be reset
to '0.'
Stopping and Starting the Oscillator
The oscillator may be stopped at any time. If the
device is going to spend a significant amount of
time on the shelf, the oscillator can be turned off to
minimize current drain on the battery. The STOP
Bit is located at Bit D7 within the Seconds Register
(7FFF9h). Setting it to a '1' stops the oscillator.
When reset to a '0,' the M48T201Y/V oscillator
starts within one second.
Note:
It is not necessary to set the WRITE Bit
when setting or resetting the FREQUENCY TEST
Bit (FT) or the STOP Bit (ST).
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