- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄359067 > M48TY-85MH1 (意法半導(dǎo)體) 3.3V-5V TIMEKEEPER CONTROLLER PDF資料下載
參數(shù)資料
| 型號(hào)： | M48TY-85MH1 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 3.3V-5V TIMEKEEPER CONTROLLER |
| 中文描述： | 3.3 - 5V的計(jì)時(shí)控制器 |
| 文件頁(yè)數(shù)： | 13/33頁(yè) |
| 文件大?。?/td> | 477K |
| 代理商： | M48TY-85MH1 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)當(dāng)前第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)
13/33
M48T201Y, M48T201V
Data Retention Mode
With valid V
CC
applied, the M48T201Y/V can be
accessed as described above with READ or
WRITE cycles. Should the supply voltage decay,
the M48T201Y/V will automatically deselect, write
protecting itself (and any external SRAM) when
V
CC
falls between V
PFD
(max) and V
PFD
(min).
This is accomplished by internally inhibiting ac-
cess to the clock registers via the E signal. At this
time, the Reset pin (RST) is driven active and will
remain active until V
CC
returns to nominal levels.
External RAM access is inhibited in a similar man-
ner by forcing E
CON
to a high level. This level is
within 0.2V of the V
BAT
. E
CON
will remain at this
level as long as V
CC
remains at an out-of-toler-
ance condition. When V
CC
falls below the level of
the battery (V
BAT
), power input is switched from
the V
CC
pin to the SNAPHAT
battery and the
clock registers are maintained from the attached
battery supply. External RAM is also powered by
the SNAPHAT battery. All outputs except G
CON
,
E
CON
, RST, IRQ/FT and V
OUT
, become high im-
pedance. The V
OUT
pin is capable of supplying
100μA of current to the attached memory with less
than 0.3V drop under this condition. On power up,
when V
CC
returns to a nominal value, write protec-
tion continues for 200ms (max) by inhibiting E
CON
.
The RST signal also remains active during this
time (see
Figure 15., page 27
).
Note:
Most low power SRAMs on the market to-
day can be used with the M48T201Y/V TIME-
KEEPER
SUPERVISOR. There are, however
some criteria which should be used in making the
final choice of an SRAM to use.
The SRAM must be designed in a way where the
chip enable input disables all other inputs to the
SRAM. This allows inputs to the M48T201Y/V and
SRAMs to be “Don't care” once V
CC
falls below
V
PFD
(min). The SRAM should also guarantee
data retention down to V
CC
= 2.0V. The chip en-
able access time must be sufficient to meet the
system needs with the chip enable (and output en-
able) output propagation delays included.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M48TY-85MH1TR | 3.3V-5V TIMEKEEPER CONTROLLER |
| M48TY-85PM1 | 3.3V-5V 1 Mbit 128Kb x8 TIMEKEEPER SRAM |
| M48Z02 | 16 Kbit 2Kb x 8 ZEROPOWER SRAM |
| M48Z02-150PC1 | FILTER SAW BANDPASS 44MHZ |
| M48Z02-150PC1TR | FILTER SAW BANDPASS 44MHZ 5-SIP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M48TY-85MH1TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:3.3V-5V TIMEKEEPER CONTROLLER |
| M48TY-85PM1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:3.3V-5V 1 Mbit 128Kb x8 TIMEKEEPER SRAM |
| M48Z02 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5V, 16Kbit (2Kb x 8) ZEROPOWER SRAM |
| M48Z02_07 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5V, 16Kbit (2Kb x 8) ZEROPOWER SRAM |
| M48Z02_10 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5 V, 16 Kbit (2 Kb x 8) ZEROPOWER? SRAM |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。