參數(shù)資料
型號(hào)： M48TMH1TR
廠商： 意法半導(dǎo)體
英文描述： 5V PC REAL TIME CLOCK
中文描述： 5V的電腦實(shí)時(shí)時(shí)鐘
文件頁(yè)數(shù)： 15/23頁(yè)
文件大?。?/td> 163K
代理商： M48TMH1TR
15/23
M48T86
UIP. Update in Progress
The Update in Progress (UIP) bit is a status flag
that can be monitored. When the UIP bit is one,
the update transfer will soon occur. When UIP isa
zero, the update transfer will not occur for at least
244μs. The time, calendar, and alarm information
in RAM is fully available for access when the UIP
bit is zero. The UIP bit is read only and is not af-
fected by RST. Writing the SET bit in Register B to
a "1" inhibits any update transfer and clears the
UIP status bit.
OSC0, OSC1, OSC2. Oscillator Control
These three bits are used to control the oscillator
and reset the countdown chain. A pattern of "010"
enables operation by turning on the oscillator and
enabling the divider chain. A pattern of 11X turns
the oscillator on, but keeps the frequency divider
disabled. When "010" is written, the first update
begins after 500ms.
RS3, RS2, RS1, RS0
These four rate-selection bits select one of the 13
taps on the 15-stage divider or disable the divider
output. The tap selected may be used to generate
an output square wave (SQW pin) and/or a period-
ic interrupt. The user may do one of the following:
1. Enable the interrupt with the PIE bit;
or
2. Enable the SQW output with the SQWE bit;
or
3. Enable both at the same time and same rate;
or
4. Enable neither.
Table 10 lists the periodic interrupt rates and the
square wave frequencies that may be chosen with
the RS bits. These four read/write bits are not af-
fected by RST.
REGISTER A
MSB
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
UIP
OSC2
OSC1
OSC0
RS3
RS2
RS1
RS0
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