參數(shù)資料
型號(hào)： M48T35AV-10MH1F
廠商： STMICROELECTRONICS
元件分類： 時(shí)鐘/數(shù)據(jù)恢復(fù)及定時(shí)提取
英文描述： 0 TIMER(S), REAL TIME CLOCK, PDSO28
封裝： 0.330 INCH, ROHS COMPLIANT, PLASTIC, SOH-28
文件頁(yè)數(shù)： 3/29頁(yè)
文件大?。?/td> 512K
代理商： M48T35AV-10MH1F
M48T35AV
Operation modes
Doc ID 6845 Rev 8
Table 4.
WRITE mode AC characteristics
2.3
Data retention mode
With valid VCC applied, the M48T35AV operates as a conventional BYTEWIDE static
RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write
protecting itself when VCC falls within the VPFD (max), VPFD (min) window (see Figure 13,
Table 10, and Table 11 on page 21). All outputs become high impedance, and all inputs are
treated as “don't care.”
Note:
A power failure during a WRITE cycle may corrupt data at the currently addressed location,
but does not jeopardize the rest of the RAM's content. At voltages below VPFD (min), the
user can be assured the memory will be in a write protected state, provided the VCC fall time
is not less than tF. The M48T35AV may respond to transient noise spikes on VCC that reach
into the deselect window during the time the device is sampling VCC. Therefore, decoupling
of the power supply lines is recommended.
When VCC drops below VSO, the control circuit switches power to the internal battery which
preserves data and powers the clock. The internal button cell will maintain data in the
M48T35AV for an accumulated period of at least 7 years when VCC is less than VSO. As
system power returns and VCC rises above VSO, the battery is disconnected and the power
supply is switched to external VCC. Write protection continues until VCC reaches VPFD (min)
plus trec (min). E should be kept high as VCC rises past VPFD (min) to prevent inadvertent
WRITE cycles prior to processor stabilization. Normal RAM operation can resume trec after
VCC exceeds VPFD (max).
Symbol
Parameter(1)
1.
Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 3.0 to 3.6 V (except where noted).
M48T35AV
Unit
Min
Max
tAVAV
WRITE cycle time
100
ns
tAVWL
Address valid to WRITE enable low
0
ns
tAVEL
Address valid to chip enable low
0
ns
tWLWH
WRITE enable pulse width
80
ns
tELEH
Chip enable low to chip enable high
80
ns
tWHAX
WRITE enable high to address transition
10
ns
tEHAX
Chip enable high to address transition
10
ns
tDVWH
Input valid to WRITE enable high
50
ns
tDVEH
Input valid to chip enable high
50
ns
tWHDX
WRITE enable high to input transition
5
ns
tEHDX
Chip enable high to input transition
5
ns
tWLQZ
(2)(3)
2.
CL = 5 pF.
3.
If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
WRITE enable low to output Hi-Z
50
ns
tAVWH
Address valid to WRITE enable high
80
ns
tAVEH
Address valid to chip enable high
80
ns
tWHQX
WRITE enable high to output transition
10
ns
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M48T35AV-10MH1TR 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:256 Kbit 32Kb x8 TIMEKEEPER SRAM
M48T35AV-10MH6 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:256 Kbit 32Kb x8 TIMEKEEPER SRAM
M48T35AV-10MH6E 功能描述:NVRAM 256K (32Kx8) 100ns BULK RoHS:否 制造商:Maxim Integrated 數(shù)據(jù)總線寬度:8 bit 存儲(chǔ)容量:1024 Kbit 組織:128 K x 8 接口類型:Parallel 訪問時(shí)間:70 ns 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 工作電流:85 mA 最大工作溫度:+ 70 C 最小工作溫度:0 C 封裝 / 箱體:EDIP 封裝:Tube
M48T35AV-10MH6F 功能描述:NVRAM 256K (32Kx8) 100ns RoHS:否 制造商:Maxim Integrated 數(shù)據(jù)總線寬度:8 bit 存儲(chǔ)容量:1024 Kbit 組織:128 K x 8 接口類型:Parallel 訪問時(shí)間:70 ns 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 工作電流:85 mA 最大工作溫度:+ 70 C 最小工作溫度:0 C 封裝 / 箱體:EDIP 封裝:Tube
M48T35AV-10MH6TR 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:256 Kbit 32Kb x8 TIMEKEEPER SRAM
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