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參數(shù)資料
| 型號： | M485L1624FT0-CA2 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | DDR SDRAM SODIMM |
| 中文描述： | 的DDR SDRAM SODIMM |
| 文件頁數(shù)： | 11/20頁 |
| 文件大小： | 264K |
| 代理商： | M485L1624FT0-CA2 |
DDR SDRAM
128MB, 256MB SODIMM
Rev. 1.2 March 2004
AC Operating Conditions
Parameter/Condition
Symbol
Min
Max
Unit
Note
Input High (Logic 1) Voltage, DQ, DQS and DM signals
Input Low (Logic 0) Voltage, DQ, DQS and DM signals.
Input Differential Voltage, CK and CK inputs
Input Crossing Point Voltage, CK and CK inputs
VIH(AC)
VIL(AC)
VID(AC)
VIX(AC)
VREF + 0.31
V
V
V
V
3
3
1
2
VREF - 0.31
VDDQ+0.6
0.5*VDDQ+0.2
0.7
0.5*VDDQ-0.2
Note 1. VID is the magnitude of the difference between the input level on CK and the input on CK.
2. The value of V
IX
is expected to equal 0.5*V
DDQ
of the transmitting device and must track variations in the DC level of the same.
3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in simula-
tion. the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited 20MHz.
Output Load Circuit (SSTL_2)
Output
Z0=50
C
LOAD
=30pF
V
REF
=0.5*V
DDQ
R
T
=50
V
tt
=0.5*V
DDQ
Input/Output Capacitance
(VDD=2.5V, VDDQ=2.5V, TA= 25
°
C, f=1MHz)
Parameter
Symbol
M470L1624FT0
Min
41
34
34
25
6
6
-
M470L3224FT0
Min
49
42
42
25
6
6
-
M485L1624FT0
Min
41
34
34
25
6
6
6
Unit
Max
45
38
38
30
7
7
-
Max
57
50
50
30
7
7
-
Max
45
38
38
30
7
7
7
Input capacitance(A0 ~ A12, BA0 ~ BA1,RAS,CAS,WE )
Input capacitance(CKE0, CKE1)
Input capacitance( CS0, CS1)
Input capacitance( CLK0, CLK1,CLK2)
Input capacitance(DM0~DM7,DM8(for ECC))
Data & DQS input/output capacitance(DQ0~DQ63)
Data input/output capacitance (CB0~CB7)
CIN1
CIN2
CIN3
CIN4
CIN5
Cout1
Cout2
pF
pF
pF
pF
pF
pF
pF
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| M485L1624FT0-CB0 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:DDR SDRAM SODIMM |
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