參數(shù)資料
型號(hào): M41T81
廠商: 意法半導(dǎo)體
英文描述: SERIAL ACCESS RTC WITH ALARMS
中文描述: 串行訪問時(shí)鐘用鬧鐘
文件頁數(shù): 14/28頁
文件大?。?/td> 386K
代理商: M41T81
M41T81
14/28
Data Retention Mode
With valid V
CC
applied, the M41T81 can be ac-
cessed as described above with READ or WRITE
Cycles. Should the supply voltage decay, the pow-
er input will be switched from the V
CC
pin to the
battery when V
CC
falls below the Battery Back-up
Switchover Voltage (V
SO
). At this time the clock
registers will be maintained by the attached bat-
tery supply. As V
CC
continues to fall, the M41T81
will pass through the Register Bit Reset Voltage
(V
RST
) threshold, not only write protecting itself,
but also resetting certain Control Bits (see Table
13, page 21). On power-up, when V
CC
returns to a
nominal value, write protection continues for t
REC
.
For a further, more detailed review of lifetime cal-
culations, please see Application Note AN1012.
Figure 17. Power Down/Up Mode AC Waveforms
Table 8. Power Down/Up AC Characteristics
Note: 1. V
CC
fall time should not exceed 5mV/μs.
2. Valid for Ambient Operating Temperature: T
A
= –40 to 85°C; V
CC
= 2.0 to 5.5V (except where noted).
Table 9. Power Down/Up Trip Points DC Characteristics
Note: 1. All voltages referenced to V
SS
.
2. Valid for Ambient Operating Temperature: T
A
= –40 to 85°C; V
CC
= 2.0 to 5.5V (except where noted).
Symbol
Parameter
(1,2)
Min
Typ
Max
Unit
t
PD
SCL and SDA at V
IH
before Power Down
0
nS
t
REC
SCL and SDA at V
IH
after Power Up
10
μS
Sym
Parameter
(1,2)
Min
Typ
Max
Unit
V
SO
Battery Back-up Switchover Voltage
V
BAT
– 0.80
V
BAT
– 0.50
V
BAT
– 0.30
V
V
RST
Register Bit Reset Voltage
1.1
2.0
V
AI00596
VCC
tREC
tPD
VSO
SDA
SCL
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