參數(shù)資料
型號: M41T80M6
廠商: 意法半導體
英文描述: SWITCH, VR, ILLUM, GREEN/BLUE; Switch function type:SPNO; Voltage, contact DC max:24V; Temp, op. max:70(degree C); Temp, op. min:-30(degree C); Diameter, panel cut-out:19.2mm; Length / Height, external:31mm; Depth, external:30.3mm; RoHS Compliant: Yes
中文描述: 串行訪問時鐘用鬧鐘
文件頁數(shù): 12/20頁
文件大小: 122K
代理商: M41T80M6
M41T80
12/20
CLOCK OPERATION
The M41T80 is driven by a quartz-controlled oscil-
lator with a nominal frequency of 32,768Hz. The
accuracy of the Real Time Clock depends on the
frequency of the quartz crystal that is used as the
time-base for the RTC.
The 20-byte Register Map (see Table 8, page 13)
is used to both set the clock and to read the date
and time from the clock, in a binary coded decimal
format. Tenths/Hundredths of Seconds, Seconds,
Minutes, and Hours are contained within the first
four registers.
Note:
A WRITE to any clock register will result in
the Tenths/Hundredths of Seconds being reset to
“00,” and Tenths/Hundredths of Seconds cannot
be written to any value other than “00.”
Bits D6 and D7 of Clock Register 03h (Century/
Hours Register) contain the CENTURY ENABLE
Bit (CEB) and the CENTURY Bit (CB). Setting
CEB to a '1' will cause CB to toggle, either from '0'
to '1' or from '1' to '0' at the turn of the century (de-
pending upon its initial state). If CEB is set to a '0,'
CB will not toggle. Bits D0 through D2 of Register
04h contain the Day (day of week). Registers 05h,
06h, and 07h contain the Date (day of month),
Month and Years. The ninth clock register is the
Control Register. Bit D7 of Register 01h contains
the STOP Bit (ST). Setting this bit to a '1' will cause
the oscillator to stop. If the device is expected to
spend a significant amount of time on the shelf, the
oscillator may be stopped to reduce current drain.
When reset to a '0' the oscillator restarts within
four seconds (typically one second).
The eight Clock Registers may be read one byte at
a time, or in a sequential block. Provision has been
made to assure that a clock update does not occur
while any of the eight clock addresses are being
read. If a clock address is being read, an update of
the clock registers will be halted. This will prevent
a transition of data during the READ.
TIMEKEEPER
Registers
The M41T80 offers 20 internal registers which
contain Clock, Alarm, 32kHz, Flag, Square Wave,
and Control data. These registers are memory lo-
cations which contain external (user accessible)
and internal copies of the data (usually referred to
as BiPORT
TIMEKEEPER cells). The external
copies are independent of internal functions ex-
cept that they are updated periodically by the si-
multaneous transfer of the incremented internal
copy. The internal divider (or clock) chain will be
reset upon the completion of a WRITE to any clock
address.
The system-to-user transfer of clock data will be
halted whenever the address being read is a clock
address (00h to 07h). The update will resume ei-
ther due to a Stop Condition or when the pointer
increments to any non-clock address (08h-13h).
TIMEKEEPER and Alarm Registers store data in
BCD. Control, 32kHz, and Square Wave Registers
store data in Binary Format.
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