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參數資料
| 型號： | M41T56MH6F |
| 廠商： | 意法半導體 |
| 英文描述： | 512 bit (64 bit x8) Serial Access TIMEKEEPER SRAM |
| 中文描述： | 512位（64位× 8）串行SRAM的訪問計時器 |
| 文件頁數： | 8/24頁 |
| 文件大?。?/td> | 346K |
| 代理商： | M41T56MH6F |
M41T56
8/24
Figure 9. Bus Timing Requirements Sequence
Table 2. AC Characteristics
Note: 1. Valid for Ambient Operating Temperature: T
A
= –40 to 85°C; V
CC
= 4.5 to 5.5V (except where noted).
2. Transmitter must internally provide a hold time to bridge the undefined region (300ns max.) of the falling edge of SCL.
Symbol
Parameter
(1)
Min
Max
Unit
f
SCL
SCL Clock Frequency
0
100
kHz
t
LOW
Clock Low Period
4.7
μs
t
HIGH
Clock High Period
4
μs
t
R
SDA and SCL Rise Time
1
μs
t
F
SDA and SCL Fall Time
300
ns
t
HD:STA
START Condition Hold Time
(after this period the first clock pulse is generated)
4
μs
t
SU:STA
START Condition Setup Time
(only relevant for a repeated start condition)
4.7
μs
t
SU:DAT
Data Setup Time
250
ns
t
HD:DAT(2)
Data Hold Time
0
μs
t
SU:STO
STOP Condition Setup Time
4.7
μs
t
BUF
Time the bus must be free before a new transmission can start
4.7
μs
AI00589
SDA
P
tSU:STO
tSU:STA
tHD:STA
SR
SCL
tSU:DAT
tF
tHD:DAT
tR
tHIGH
tLOW
tHD:STA
tBUF
S
P
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