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參數(shù)資料
| 型號： | LTC4264IDE#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 3/24頁 |
| 文件大小： | 0K |
| 描述： | IC CNTRLR PD INTERFACE 12-DFN |
| 產(chǎn)品培訓模塊： | Power over Ethernet |
| 標準包裝： | 91 |
| 控制器類型： | 以太網(wǎng)供電控制器（POE） |
| 接口： | IEEE 802.3af |
| 電流 - 電源： | 3mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 12-WFDFN 裸露焊盤 |
| 供應商設備封裝： | 12-DFN（4x3） |
| 包裝： | 管件 |
LTC4264
11
4264f
APPLICATIONS INFORMATION
During classication, the PSE presents a xed voltage
between –15.5V and –20.5V to the PD (Figure 6). With
the input voltage in this range, the LTC4264 asserts a load
current from the GND pin through the RCLASS resistor. The
magnitude of the load current is set with the selection of
the RCLASS resistor. The resistor value associated with
each class is shown in Table 2.
Table 2. Summary of IEEE 802.3af Power Classications and
LTC4264 RCLASS Resistor Selection
CLASS
USAGE
MAXIMUM
POWER LEVELS
AT INPUT OF PD
(W)
NOMINAL
CLASSIFICATION
LOAD CURRENT
(mA)
LTC4264
RCLASS
RESISTOR
(
Ω, 1%)
0
Default
0.44 to 12.95
<5
Open
1
Optional
0.44 to 3.84
10.5
124
2
Optional
3.84 to 6.49
18.5
69.8
3
Optional
6.49 to 12.95
28
45.3
4
Reserved by IEEE. See Apps
40
30.9
5
Undened IEEE. See Apps
56
22.1
A substantial amount of power is dissipated in the LTC4264
during classication. The IEEE 802.3af specication limits
the classication time to 75ms in order avoid excessive
heating. The LTC4264 is designed to handle the power
dissipation during the probe period. If the PSE probing
exceeds 75ms, the LTC4264 may overheat. In this situa-
tion, the thermal protection circuit will engage and disable
the classication current source, protecting the LTC4264
from damage. When the die cools, classication is auto-
matically resumed.
Classication presents a challenging stability problem
for the PSE due to the wide range of loads possible. The
LTC4264 has been designed to avoid PSE interoperability
problems by maintaining a positive I-V slope throughout
the signature and classication ranges up to UVLO turn-
on as shown in Figure 6b. The positive I-V slope avoids
areas of negative resistance and helps prevent the PSE
from power cycling or getting “stuck” during signature
or classication probing. In the event a PSE overshoots
beyond the classication voltage range, the available load
current aids in returning the PD back into the classication
voltage range. (The PD input may otherwise be “trapped”
by a reverse-biased diode bridge and the voltage held by
the 0.1F capacitor.) By gently ramping the classication
current on and maintaining a positive I-V slope until UVLO
turn-on, the LTC4264 provides a well behaved load, as-
suring interoperability with any PSE.
GND
RCLASS
VIN
LTC4264
CONSTANT
LOAD
CURRENT
INTERNAL
TO LTC4264
4264 F06a
RCLASS
CURRENT PATH
V
PD
PSE
PSE CURRENT MONITOR
PSE
PROBING
VOLTAGE
SOURCE
–15.5V TO –20.5V
INPUT VOLTAGE (V)
0
INPUT
CURRENT
(mA)
–40
4264 F06b
–10
–20
–30
Figure 6a. PSE Probing PD During Classication
Figure 6b. LTC4264 Positive I-V Slope
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