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參數(shù)資料
| 型號： | LTC4264IDE#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 11/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CNTRLR PD INTERFACE 12-DFN |
| 產(chǎn)品培訓模塊： | Power over Ethernet |
| 標準包裝： | 91 |
| 控制器類型： | 以太網(wǎng)供電控制器（POE） |
| 接口： | IEEE 802.3af |
| 電流 - 電源： | 3mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 12-WFDFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 12-DFN（4x3） |
| 包裝： | 管件 |
LTC4264
19
4264f
APPLICATIONS INFORMATION
RCLASS from Table 2. If a unique load current is required,
the value of RCLASS can be calculated as:
RCLASS = 1.237V/(ILOAD – IIN_CLASS)
IIN_CLASS is the LTC4264 IC supply current during clas-
sication given in the electrical specications. The RCLASS
resistor must be 1% or better to avoid degrading the overall
accuracy of the classication circuit. Resistor power dissi-
pation will be 100mW maximum and is transient so heating
is typically not a concern. In order to maintain loop stabil-
ity, the layout should minimize capacitance at the RCLASS
node. The classication circuit can be disabled by oating
the RCLASS pin. The RCLASS pin should not be shorted to
VIN as this would force the LTC4264 classication circuit
to attempt to source very large currents. In this case, the
LTC4264 will quickly go into thermal shutdown.
GND
RS
10k
R10
100k
PWRGD
D9
MMBD4148
Q1
FMMT2222
–54V
4264 F11
TO
PSE
LTC4264
ACTIVE-LOW ENABLE
VIN
VOUT
V+
PD
LOAD
GND
RS
10k
R9
100k
PWRGD
D9
5.1V
MMBZ5231B
–54V
TO
PSE
LTC4264
ACTIVE-LOW ENABLE
VIN
VOUT
PD
LOAD
–54V
TO
PSE
ACTIVE-HIGH ENABLE
PD
LOAD
RUN
SHDN
GND
PWRGD
LTC4264
VIN
VOUT
Power Good Interface
The LTC4264 provides complimentary power good signals
to simplify the DC/DC converter interface. Using the power
good signal to delay converter operation until the load
capacitor is fully charged is recommended as this will help
ensure trouble free start up. The active high PWRGD pin
is controlled by an open collector transistor referenced to
VOUT while the active low PWRGD pin is controlled by a
high voltage, open-drain MOSFET referenced to VIN. The
designer has the option of using either of these signals to
enable the DC/DC converter and example interface circuits
are shown in Figure 11. When using PWRGD, diode D9
and resistor RS protects the converter shutdown pin from
excessive reverse voltage.
Figure 11. Power Good Interface Examples
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