參數(shù)資料
型號(hào)： LTC4258CGW#PBF
廠商： Linear Technology
文件頁(yè)數(shù)： 16/28頁(yè)
文件大?。?/td> 0K
描述： IC POE 802.3AF QUAD 36-SSOP
產(chǎn)品培訓(xùn)模塊： Power over Ethernet
標(biāo)準(zhǔn)包裝： 32
控制器類型： 以太網(wǎng)供電控制器（POE）
接口： IEEE 802.3af
電源電壓： 3 V ~ 4 V
電流 - 電源： 2.5mA
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 36-BSOP（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 36-SSOP
包裝： 管件
LTC4258
23
4258fb
Acknowledge
The Acknowledge signal is used for handshaking between
the master and the slave. An Acknowledge (active LOW)
generated by the slave lets the master know that the latest
byte of information was received. The corresponding SCL
clock pulse is always generated by the master. The master
releases the SDA line (HIGH) during the Acknowledge
clock pulse. The slave must pull down the SDA line during
the Acknowledge clock pulse so that it remains a stable
LOW during the HIGH period of this clock pulse. When the
master is reading from a slave device, it is the master’s
responsibility to acknowledge receipt of the data byte in
the bit that follows unless the transaction is complete. In
that case the master will decline to acknowledge and issue
the STOP condition to terminate the communication.
Write Byte Protocol
The master initiates communication to the LTC4258 with
a START condition and a 7-bit bus address followed by the
Write Bit (Wr) = 0. If the LTC4258 recognizes its own
address, it acknowledges and the master delivers the com-
mand byte, signifying to which internal LTC4258 register
the master wishes to write. The LTC4258 acknowledges
and latches the lower five bits of the command byte into its
Register Address register. Only the lower five bits of the
command byte are checked by the LTC4258; the upper
three bits are ignored. The master then delivers the data
byte. The LTC4258 acknowledges once more and latches
the data into the appropriate control register. Finally, the
master terminates the communication with a STOP condi-
tion. Upon reception of the STOP condition, the Register
Address register is cleared (see Figure 6).
Read Byte Protocol
The master initiates communication from the LTC4258
with a START condition and the same 7-bit bus address
followed by the Write Bit (Wr) = 0. If the LTC4258
recognizes its own address, it acknowledges and the
master delivers the command byte, signifying which
internal LTC4258 register it wishes to read from. The
LTC4258 acknowledges and latches the lower five bits of
the command byte into its Register Address register. At
this time the master sends a REPEATED START condition
and the same 7-bit bus address followed by the Read Bit
(Rd) = 1. The LTC4258 acknowledges and sends the
contents of the requested register. Finally, the master
declines to acknowledge and terminates communication
with a STOP condition. Upon reception of the STOP
condition, the Register Address register is cleared (see
Figure 7).
Receive Byte Protocol
Since the LTC4258 clears the Register Address register on
each STOP condition, the interrupt register (register 0)
may be read with the Receive Byte Protocol as well as with
the Read Byte Protocol. In this protocol, the master
initiates communication with the LTC4258 with a START
condition and a 7-bit bus address followed by the Read Bit
(Rd) = 1. The LTC4258 acknowledges and sends the
contents of the interrupt register. The master then de-
clines to acknowledge and terminates communication
with a STOP condition (see Figure 8).
Alert Response Address and the INT Pin
In a system where several LTC4258s share a common INT
line, the master can use the Alert Response Address (ARA)
to determine which LTC4258 initiated the interrupt.
The master initiates the ARA procedure with a START
condition and the 7-bit ARA bus address (0001100)b
followed by the Read Bit (Rd) = 1. If an LTC4258 is
asserting the INT pin, it acknowledges and sends its 7-bit
bus address (010A3A2A1A0)b and a 1 (see Figure 9). While
it is sending its address, it monitors the SDAIN pin to see
if another device is sending an address at the same time
using standard I2C bus arbitration. If the LTC4258 is
sending a 1 and reads a 0 on the SDAIN pin on the rising
edge of SCL, it assumes another device with a lower
address is sending and the LTC4258 immediately aborts
its transfer and waits for the next ARA cycle to try again.
If transfer is successfully completed, the LTC4258 will
stop pulling down the INT pin. When the INT pin is released
in this way or if a 1 is written into the Clear Interrupt pin bit
(bit 6 of register 1Ah), the condition causing the LTC4258
to pull the INT pin down must be removed before the
LTC4258 will be able to pull INT down again. This can be
done by reading and clearing the event registers or by
writing a 1 into the Clear All Interrupts bit (bit 7 of register
APPLICATIO S I FOR ATIO
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