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參數(shù)資料
| 型號： | LPC47B34X |
| 廠商： | STANDARD MICROSYSTEMS CORP |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | 128 Pin Enhanced Super I/O with LPC Interface for Consumer Applications |
| 中文描述： | MULTIFUNCTION PERIPHERAL, PQFP128 |
| 封裝： | QFP-128 |
| 文件頁數(shù)： | 146/250頁 |
| 文件大?。?/td> | 645K |
| 代理商： | LPC47B34X |
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146
PME SUPPORT
The LPC47B34x offers support for power management events (PMEs), also referred to as System
Control Interrupt (SCI) events. A power management event is indicated to the chipset via the
assertion of the nIO_PME signal. In the LPC47B34x, the nIO_PME is asserted by active transitions
on the ring indicator inputs nRI1 and nRI2, active keyboard-data edges, active mouse-data edges,
Wakeup on Specific key, Super I/O Device Interrupts, Watchdog Timer, Ring, Intrusion and
programmable edges on GPIO pins. The nIO_PME pin can be programmed to be active high or active
low via the polarity bit in the GP42 register. The output buffer type of the pin can be programmed to
be open-drain or push-pull via bit 7 of the GP42 register. The nIO_PME pin defaults to active low,
open-drain output.
PME functionality is controlled by registers in the Runtime Registers Block, which is located at the
address programmed in configuration registers 0x60 and 0x61 in Logical Device A. The PME Enable
bit in the PME Enable register, PME_EN, globally controls PME Wake-up events. When PME_EN is
inactive, the nIO_PME signal can not be asserted. When PME_EN is asserted, any wake source
whose individual PME Wake Enable register bit is asserted can cause nIO_PME to become asserted.
The PME_STS bit in the PME Status register indicates that an enabled wake source has occurred, and
if the PME_EN bit is set, asserted the nIO_PME signal. The PME Status bit is asserted by active
transitions of enabled PME Wake sources. PME_STS will become asserted independent of the state
of the global PME enable bit, PME_EN. The individual status bits in each of the PME Wake Status
registers indicates which wake source has asserted the nIO_PME signal. The individual status bits for
the PME events will become asserted independent of the state of the associated enable bit.
The following pertains to the PME status bits for each event:
The output of the status bit for each event is combined with the corresponding enable bit to set
the PME status bit.
The status bit for any pending events must be cleared in order to clear the PME_STS bit.
For the GPIO events, the polarity of the edge used to set the status bit and generate a PME is
controlled by the polarity bit of the GPIO control register. For non-inverted polarity (default) the status
bit is set on the low-to-high edge. If the EETI function is selected for a GPIO then both a high-to-low
and a low-to-high edge will set the corresponding PME status bits. Status bits are cleared on a write
of ‘1’.
See the “Keyboard and Mouse PME Generation” sub-section in the “8042 Keyboard Controller” section
for information about using the keyboard and mouse signals to generate a PME.
Pins P12 and P16 enable PME event on single high-to-low edge or on both high-to-low and low-to-
high edges. Default is single edge. P12 also has a polarity select bit in the configuration register
0xF0 in Logical Device 7. The register that selects the edge is the Edge Select register located at the
address programmed in the Base I/O Address register in the Logical Device A at an offset of 2Ch.
Refer to PME Status and Enable register 9. See the Runtime Registers sections for description on
these registers.
The PME registers are run-time registers as follows. These registers are located in system I/O space
at an offset from Runtime Registers Block, the address programmed in Logical Device A at registers
0x60 and 0x61.
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