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參數(shù)資料
| 型號(hào)： | LPC47B27X |
| 廠商： | SMSC Corporation |
| 英文描述： | Round, Jacket Mass-Terminated Cable, 3659/26 28 AWG, .050 (1.27) |
| 中文描述： | 100引腳增強(qiáng)型超的I / O LPC接口控制器 |
| 文件頁數(shù)： | 89/196頁 |
| 文件大?。?/td> | 1200K |
| 代理商： | LPC47B27X |
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SMSC LPC47B27x
- 89 -
Rev. 08-10-04
DATASHEET
with a "sluggish" system by affording a long latency period after a service request, but results in more
frequent service requests.
DMA TRANSFERS
DMA transfers are always to or from the ecpDFifo, tFifo or CFifo. DMA utilizes the standard PC DMA
services. To use the DMA transfers, the host first sets up the direction and state as in the programmed I/O
case. Then it programs the DMA controller in the host with the desired count and memory address. Lastly
it sets dmaEn to 1 and serviceIntr to 0. The ECP requests DMA transfers from the host by encoding the
nLDRQ pin. The DMA will empty or fill the FIFO using the appropriate direction and mode. When the
terminal count in the DMA controller is reached, an interrupt is generated and serviceIntr is asserted,
disabling DMA. In order to prevent possible blocking of refresh requests a DMA cycle shall not be
requested for more than 32 DMA cycles in a row. The FIFO is enabled directly by the host initiating a
DMA cycle for the requested channel, and addresses need not be valid. An interrupt is generated when a
TC cycle is received. (Note: The only way to properly terminate DMA transfers is with a TC cycle.)
DMA may be disabled in the middle of a transfer by first disabling the host DMA controller. Then setting
serviceIntr to 1, followed by setting dmaEn to 0, and waiting for the FIFO to become empty or full.
Restarting the DMA is accomplished by enabling DMA in the host, setting dmaEn to 1, followed by setting
serviceIntr to 0.
DMA Mode - Transfers from the FIFO to the Host
(Note: In the reverse mode, the peripheral may not continue to fill the FIFO if it runs out of data to transfer,
even if the chip continues to request more data from the peripheral.)
The ECP requests a DMA cycle whenever there is data in the FIFO. The DMA controller must respond to
the request by reading data from the FIFO. The ECP stops requesting DMA cycles when the FIFO
becomes empty or when a TC cycle is received, indicating that no more data is required. If the ECP stops
requesting DMA cycles due to the FIFO going empty, then a DMA cycle is requested again as soon as
there is one byte in the FIFO. If the ECP stops requesting DMA cycles due to the TC cycle, then a DMA
cycle is requested again when there is one byte in the FIFO, and serviceIntr has been re-enabled.
Programmed I/O Mode or Non-DMA Mode
The ECP or parallel port FIFOs may also be operated using interrupt driven programmed I/O. Software
can determine the writeIntrThreshold, readIntrThreshold, and FIFO depth by accessing the FIFO in Test
Mode.
Programmed I/O transfers are to the ecpDFifo at 400H and ecpAFifo at 000H or from the ecpDFifo located
at 400H, or to/from the tFifo at 400H. To use the programmed I/O transfers, the host first sets up the
direction and state, sets dmaEn to 0 and serviceIntr to 0.
The ECP requests programmed I/O transfers from the host by activating the interrupt. The programmed
I/O will empty or fill the FIFO using the appropriate direction and mode.
Note: A threshold of 16 is equivalent to a threshold of 15. These two cases are treated the same.
Programmed I/O - Transfers from the FIFO to the Host
In the reverse direction an interrupt occurs when serviceIntr is 0 and readIntrThreshold bytes are
available in the FIFO. If at this time the FIFO is full it can be emptied completely in a single burst,
otherwise readIntrThreshold bytes may be read from the FIFO in a single burst.
ReadIntrThreshold =
(16-<threshold>) data bytes in FIFO
An interrupt is generated when serviceIntr is 0 and the number of bytes in the FIFO is greater than or
equal to (16-<threshold>). (If the threshold = 12, then the interrupt is set whenever there are 4-16 bytes in
the FIFO). The host must respond to the request by reading data from the FIFO. This process is repeated
until the last byte is transferred out of the FIFO. If at this time the FIFO is full, it can be completely emptied
in a single burst, otherwise a minimum of (16-<threshold>) bytes may be read from the FIFO in a single
burst.
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