
SMSC LPC47B27x
- 66 -
Rev. 08-10-04
DATASHEET
TABLE 4 – REGISTER SUMMARY FOR AN INDIVIDUAL UART CHANNEL
REGISTER
ADDRESS
(Note 1)
ADDR = 0
DLAB = 0
ADDR = 0
DLAB = 0
ADDR = 1
DLAB = 0
REGISTER NAME
REGISTER
SYMBOL
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Receive Buffer Register (Read Only)
RBR
Data Bit 7
Data Bit 6
Data Bit 5
Data Bit 4
Data Bit 3
Data Bit 2
Data Bit 1
Data Bit 0
(Note 2)
Transmitter Holding Register (Write Only)
THR
Data Bit 7
Data Bit 6
Data Bit 5
Data Bit 4
Data Bit 3
Data Bit 2
Data Bit 1
Data Bit 0
Interrupt Enable Register
IER
0
0
0
0
Enable
MODEM
Status
Interrupt
(EMSI)
Enable
Receiver
Line
Status
Interrupt
(ELSI)
Enable
Transmitter
Holding
Register
Empty
Interrupt
(ETHREI)
Interrupt ID
Bit
Enable
Received
Data
Available
Interrupt
(ERDAI)
ADDR = 2
Interrupt Ident. Register (Read Only)
IIR
FIFOs
Enabled
(Note 6)
RCVR
Trigger
MSB
FIFOs
Enabled
(Note 6)
RCVR
Trigger LSB
0
0
Interrupt ID
Bit
(Note 6)
Interrupt
ID Bit
“0” if
Interrupt
Pending
FIFO Enable
ADDR = 2
FIFO Control Register (Write Only)
FCR
(Note 8)
Reserved
Reserved
DMA Mode
Select
(Note 7)
Parity
Enable
(PEN)
XMIT FIFO
Reset
RCVR
FIFO Reset
ADDR = 3
Line Control Register
LCR
Divisor
Latch
Access Bit
(DLAB)
Set Break
Stick Parity
Even Parity
Select
(EPS)
Number of
Stop Bits
(STB)
Word
Length
Select Bit 1
(WLS1)
Word Length
Select Bit 0
(WLS0)
Data
Terminal
Ready (DTR)
Data Ready
(DR)
ADDR = 4
MODEM Control Register
MCR
0
0
0
Loop
OUT2
(Note 4)
OUT1
(Note 4)
Request to
Send (RTS)
ADDR = 5
Line Status Register
LSR
Error in
RCVR FIFO
(Note 6)
Transmitter
Empty
(TEMT)
(Note 3)
Ring
Indicator
(RI)
Transmitter
Holding
Register
(THRE)
Break
Interrupt
(BI)
Framing
Error (FE)
Parity
Error (PE)
Overrun
Error (OE)
ADDR = 6
MODEM Status Register
MSR
Data
Carrier
Detect
(DCD)
Bit 7
Bit 7
Data Set
Ready
(DSR)
Clear to
Send (CTS)
Delta Data
Carrier
Detect
(DDCD)
Bit 3
Bit 3
Trailing
Edge Ring
Indicator
(TERI)
Bit 2
Bit 2
Delta Data
Set Ready
(DDSR)
Delta Clear
to Send
(DCTS)
ADDR = 7
ADDR = 0
DLAB = 1
ADDR = 1
DLAB = 1
Scratch Register (Note 5)
Divisor Latch (LS)
SCR
DDL
Bit 6
Bit 6
Bit 5
Bit 5
Bit 4
Bit 4
Bit 1
Bit 1
Bit 0
Bit 0
Divisor Latch (MS)
DLM
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8