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參數(shù)資料
| 型號： | LPC47B27X |
| 廠商： | SMSC Corporation |
| 英文描述： | Round, Jacket Mass-Terminated Cable, 3659/26 28 AWG, .050 (1.27) |
| 中文描述： | 100引腳增強型超的I / O LPC接口控制器 |
| 文件頁數(shù)： | 58/196頁 |
| 文件大?。?/td> | 1200K |
| 代理商： | LPC47B27X |
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SMSC LPC47B27x
- 58 -
Rev. 08-10-04
DATASHEET
INTERRUPT IDENTIFICATION REGISTER (IIR)
Address Offset = 2H, DLAB = X, READ
By accessing this register, the host CPU can determine the highest priority interrupt and its source. Four levels of
priority interrupt exist. They are in descending order of priority:
1.
Receiver Line Status (highest priority)
2.
Received Data Ready
3.
Transmitter Holding Register Empty
4.
MODEM Status (lowest priority)
Information indicating that a prioritized interrupt is pending and the source of that interrupt is stored in the Interrupt
Identification Register (refer to Interrupt Control Table). When the CPU accesses the IIR, the Serial Port freezes all
interrupts and indicates the highest priority pending interrupt to the CPU. During this CPU access, even if the Serial Port
records new interrupts, the current indication does not change until access is completed. The contents of the IIR are
described below.
Bit 0
This bit can be used in either a hardwired prioritized or polled environment to indicate whether an interrupt is pending.
When bit 0 is a logic "0", an interrupt is pending and the contents of the IIR may be used as a pointer to the appropriate
internal service routine. When bit 0 is a logic "1", no interrupt is pending.
Bits 1 and 2
These two bits of the IIR are used to identify the highest priority interrupt pending as indicated by the Interrupt Control
Table.
Bit 3
In non-FIFO mode, this bit is a logic "0". In FIFO mode this bit is set along with bit 2 when a timeout interrupt is pending.
Bits 4 and 5
These bits of the IIR are always logic "0".
Bits 6 and 7
These two bits are set when the FIFO CONTROL Register bit 0 equals 1.
Table 29 - Interrupt Control
FIFO
MODE
ONLY
REGISTER
INTERRUPT SET AND RESET FUNCTIONS
BIT 3
BIT 2
BIT 1
BIT 0
LEVEL
TYPE
INTERRUPT
IDENTIFICATION
PRIORITY
INTERRUPT
INTERRUPT
SOURCE
INTERRUPT
RESET
CONTROL
-
Reading the Line
Status Register
0
0
0
1
0
1
1
0
Highest
-
None
Receiver Line
Status
None
Overrun Error,
Parity Error,
Framing Error or
Break Interrupt
Receiver Data
Available
0
1
0
0
Second
Received Data
Available
Read Receiver
Buffer or the FIFO
drops below the
trigger level.
Reading the
Receiver Buffer
Register
1
1
0
0
Second
Character
Timeout
Indication
No Characters
Have Been
Removed From or
Input to the RCVR
FIFO during the
last 4 Char times
and there is at
least 1 char in it
during this time
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