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參數(shù)資料
| 型號： | LPC47B27X |
| 廠商： | SMSC Corporation |
| 英文描述： | Round, Jacket Mass-Terminated Cable, 3659/26 28 AWG, .050 (1.27) |
| 中文描述： | 100引腳增強型超的I / O LPC接口控制器 |
| 文件頁數(shù)： | 54/196頁 |
| 文件大?。?/td> | 1200K |
| 代理商： | LPC47B27X |
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SMSC LPC47B27x
- 54 -
Rev. 08-10-04
DATASHEET
Table 27 - Effects of WGATE and GAP Bits
GAP
MODE
0
1
0
1
Perpendicular
(1 Mbps)
WGATE
0
0
1
1
LENGTH OF
GAP2 FORMAT
FIELD
22 Bytes
22 Bytes
22 Bytes
41 Bytes
PORTION OF
GAP 2
WRITTEN BY
WRITE DATA
OPERATION
0 Bytes
19 Bytes
0 Bytes
38 Bytes
Conventional
Perpendicular
(500 Kbps)
Reserved
(Conventional)
LOCK
In order to protect systems with long DMA latencies against older application software that can disable the FIFO the
LOCK Command has been added. This command should only be used by the FDC routines, and application software
should refrain from using it. If an application calls for the FIFO to be disabled then the CONFIGURE command should
be used.
The LOCK command defines whether the EFIFO, FIFOTHR, and PRETRK parameters of the CONFIGURE command
can be RESET by the DOR and DSR registers. When the LOCK bit is set to logic "1" all subsequent "software RESETS
by the DOR and DSR registers will not change the previously set parameters to their default values. All "hardware"
RESET from the nPCI_RESET pin will set the LOCK bit to logic "0" and return the EFIFO, FIFOTHR, and PRETRK to
their default values. A status byte is returned immediately after issuing a LOCK command. This byte reflects the value
of the LOCK bit set by the command byte.
ENHANCED DUMPREG
The DUMPREG command is designed to support system run-time diagnostics and application software development
and debug. To accommodate the LOCK command and the enhanced PERPENDICULAR MODE command the eighth
byte of the DUMPREG command has been modified to contain the additional data from these two commands.
COMPATIBILITY
The LPC47B27x was designed with software compatibility in mind. It is a fully backwards- compatible solution with the
older generation 765A/B disk controllers. The FDC also implements on-board registers for compatibility with the PS/2, as
well as PC/AT and PC/XT, floppy disk controller subsystems. After a hardware reset of the FDC, all registers, functions
and enhancements default to a PC/AT, PS/2 or PS/2 Model 30 compatible operating mode, depending on how the
IDENT and MFM bits are configured by the system BIOS.
DIRECT SUPPORT FOR TWO FLOPPY DRIVES
The nMTR1 function is on pin 43. nMTR1 is an alternate function on the GP22 pin. Pin 43 has the IO12 buffer type.
The nMTR1 function is selectable as open drain or push pull as nMTR0 is through bit 6 of the FDD Mode Register in
CRF0 of LD 0. This overrides the selection of the output type through bit 7 of the GPIO control register. It is also
controlled by bit 7 of the FDD Mode Register.
The nDS1 function is on pin 42. nDS1 is an alternate function on the GP21 pin. Pin 42 has IO12 buffer type.
The nDS1 function is selectable as open drain or push pull as nDS0 is through bit 6 of the FDD Mode Register in
CRF0 of Logical Device 0. This overrides the selection of the output type through bit 7 of the GPIO control register.
It is also controlled by bit 7 of the FDD Mode register.
See the Runtime Registers section for register information.
Disk Change Support for Second Floppy
Bit[1] in the Force Disk Change register supports the second floppy. Setting either of the Force Disk Change bits
active forces the internal FDD nDSKCHG active when the appropriate drive has been selected. The Force Disk
Change register is defined in the Runtime Registers section.
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