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參數(shù)資料
| 型號： | LPC47B27X |
| 廠商： | SMSC Corporation |
| 英文描述： | Round, Jacket Mass-Terminated Cable, 3659/26 28 AWG, .050 (1.27) |
| 中文描述： | 100引腳增強(qiáng)型超的I / O LPC接口控制器 |
| 文件頁數(shù)： | 20/196頁 |
| 文件大小： | 1200K |
| 代理商： | LPC47B27X |
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SMSC LPC47B27x
- 20 -
Rev. 08-10-04
DATASHEET
LPC Cycles
The following cycle types are supported by the LPC protocol.
Cycle Type
I/O Write
I/O Read
DMA Write
DMA Read
LPC47B27x ignores cycles that it does not support.
Field Definitions
The data transfers are based on specific fields that are used in various combinations, depending on the cycle type.
These fields are driven onto the LAD[3:0] signal lines to communicate address, control and data information over the
LPC bus between the host and the LPC47B27x. See the
Low Pin Count (LPC) Interface Specification
Revision 1.0
from Intel, Section 4.2 for definition of these fields.
nLFRAME Usage
nLFRAME is used by the host to indicate the start of cycles and the termination of cycles due to an abort or time-out
condition. This signal is to be used by the LPC47B27x to know when to monitor the bus for a cycle.
This signal is used as a general notification that the LAD[3:0] lines contain information relative to the start or stop of a
cycle, and that the LPC47B27x monitors the bus to determine whether the cycle is intended for it. The use of
nLFRAME allows the LPC47B27x to enter a lower power state internally. There is no need for the LPC47B27x to
monitor the bus when it is inactive, so it can decouple its state machines from the bus, and internally gate its clocks.
When the LPC47B27x samples nLFRAME active, it immediately stops driving the LAD[3:0] signal lines on the next
clock and monitor the bus for new cycle information.
The nLFRAME signal functions as described in the Low Pin Count (LPC) Interface Specification Revision 1.0.
I/O Read and Write Cycles
The LPC47B27x is the target for I/O cycles. I/O cycles are initiated by the host for register or FIFO accesses, and will
generally have minimal Sync times. The minimum number of wait-states between bytes is 1. EPP cycles will depend
on the speed of the external device, and may have much longer Sync times.
Data transfers are assumed to be exactly 1-byte. If the CPU requested a 16 or 32-bit transfer, the host will break it
up into 8-bit transfers.
See the
Low Pin Count (LPC) Interface Specification
Reference, Section 5.2, for the sequence of cycles for the I/O
Read and Write cycles.
DMA Read and Write Cycles
DMA read cycles involve the transfer of data from the host (main memory) to the LPC47B27x. DMA write cycles
involve the transfer of data from the LPC47B27x to the host (main memory). Data will be coming from or going to a
FIFO and will have minimal Sync times. Data transfers to/from the LPC47B27x are 1, 2 or 4 bytes.
See the
Low Pin Count (LPC) Interface Specification
Reference, Section 6.4, for the field definitions and the
sequence of the DMA Read and Write cycles.
DMA Protocol
DMA on the LPC bus is handled through the use of the nLDRQ lines from the LPC47B27x and special encodings on
LAD[3:0] from the host.
The DMA mechanism for the LPC bus is described in the Low Pin Count (LPC) Interface Specification Revision 1.0.
Transfer Size
1 Byte
1 Byte
1 Byte
1 Byte
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