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參數(shù)資料
| 型號(hào)： | LPC47B27X |
| 廠商： | SMSC Corporation |
| 英文描述： | Round, Jacket Mass-Terminated Cable, 3659/26 28 AWG, .050 (1.27) |
| 中文描述： | 100引腳增強(qiáng)型超的I / O LPC接口控制器 |
| 文件頁數(shù)： | 161/196頁 |
| 文件大小： | 1200K |
| 代理商： | LPC47B27X |
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SMSC LPC47B27x
- 161 -
Rev. 08-10-04
DATASHEET
Note:
An Interrupt is activated by setting the Interrupt Request Level Select 0 register to a non-zero
value AND :
For the FDC logical device by setting DMAEN, bit D3 of the Digital Output Register.
For the PP logical device by setting IRQE, bit D4 of the Control Port and in addition
For the PP logical device in ECP mode by clearing serviceIntr, bit D2 of the ecr.
For the Serial Port logical device by setting any combination of bits D0-D3 in the IER
and by setting the OUT2 bit in the UART's Modem Control (MCR) Register.
For the KYBD by (refer to the KYBD controller section of this spec).
For MPU-401 logical device (refer to the MPU-401 section of this spec).
IRQs are disabled if not used/selected by any Logical Device. Refer to Note A.
Note: nSMI must be disabled to use IRQ2.
Note:
All IRQ’s are available in Serial IRQ mode.
Note 1: The default value of the Primary Interrupt Select register for logical device 0 is 0x06.
Table 67 - DMA Channel Select Configuration Register Description
NAME
REG INDEX
DMA Channel
Select
Default=0x02 or
0x04
(Note 1)
on VCC POR,
VTR POR,
HARD RESET
and
SOFT RESET
Note:
A DMA channel is activated by setting the DMA Channel Select register to [0x01-0x03] AND :
For the FDC logical device by setting DMAEN, bit D3 of the Digital Output Register.
For the PP logical device in ECP mode by setting dmaEn, bit D3 of the ecr.
For the UART 2 logical device, by setting the DMA Enable bit. Refer to the IrCC specification.
Note:
DMA channels are disabled if not used/selected by any Logical Device. Refer to Note A.
Note 1: The default value of the DMA Channel Select register for logical device 0 (FDD) is 0x02 and for
logical device 3 and 5 is 0x04.
Note A. Logical Device IRQ and DMA Operation
1.
IRQ and DMA Enable and Disable: Any time the IRQ or DMA channel for a logical block is
disabled by a register bit in that logical block, the IRQ and/or DMA channel must be disabled. This is in
addition to the IRQ and DMA channel disabled by the Configuration Registers (active bit or address not
valid).
a.
FDC: For the following cases, the IRQ and DMA channel used by the FDC are disabled.
Digital Output Register (Base+2) bit D3 (DMAEN) set to "0".
The FDC is in power down (disabled).
b.
Serial Ports:
Modem Control Register (MCR) Bit D2 (OUT2) - When OUT2 is a logic "0", the serial port
interrupt is disabled.
Disabling DMA Enable bit, disables DMA for UART2. Refer to the IrCC specification.
c.
Parallel Port:
I.
SPP and EPP modes: Control Port (Base+2) bit D4 (IRQE) set to "0", IRQ is
disabled.
ii.
ECP Mode:
(1)
(DMA) dmaEn from ecr register. See table.
(2)
IRQ - See table.
MODE
(FROM ECR REGISTER)
CONTROLLED BY
000
PRINTER
001
SPP
Note:
DEFINITION
STATE
C
0x74 (R/W)
Bits[2:0] select the DMA Channel.
0x00= Reserved
0x01= DMA1
0x02= DMA2
0x03= DMA3
0x04-0x07= No DMA active
IRQ
DMA
CONTROLLED BY
dmaEn
dmaEn
IRQE
IRQE
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