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參數(shù)資料
| 型號： | LPC47B27X |
| 廠商： | SMSC Corporation |
| 英文描述： | Round, Jacket Mass-Terminated Cable, 3659/26 28 AWG, .050 (1.27) |
| 中文描述： | 100引腳增強型超的I / O LPC接口控制器 |
| 文件頁數(shù)： | 101/196頁 |
| 文件大?。?/td> | 1200K |
| 代理商： | LPC47B27X |
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SMSC LPC47B27x
- 101 -
Rev. 08-10-04
DATASHEET
Keyboard Data Write
This is an 8 bit write only register. When written, the C/D status bit of the status register is cleared to zero
and the IBF bit is set.
Keyboard Data Read
This is an 8 bit read only register. If enabled by "ENABLE FLAGS", when read, the KIRQ output is cleared
and the OBF flag in the status register is cleared. If not enabled, the KIRQ and/or AUXOBF1 must be
cleared in software.
Keyboard Command Write
This is an 8 bit write only register. When written, the C/D status bit of the status register is set to one and
the IBF bit is set.
Keyboard Status Read
This is an 8 bit read only register. Refer to the description of the Status Register for more information.
CPU-to-Host Communication
The LPC47B27x CPU can write to the Output Data register via register DBB. A write to this register
automatically sets Bit 0 (OBF) in the Status register. See Table 52.
Table 52 - Host Interface Flags
8042 INSTRUCTION
OUT DBB
Set OBF, and, if enabled, the KIRQ output signal goes high
Host-to-CPU Communication
The host system can send both commands and data to the Input Data register. The CPU differentiates
between commands and data by reading the value of Bit 3 of the Status register. When bit 3 is "1", the
CPU interprets the register contents as a command. When bit 3 is "0", the CPU interprets the register
contents as data. During a host write operation, bit 3 is set to "1" if SA2 = 1 or reset to "0" if SA2 = 0.
KIRQ
If "EN FLAGS" has been executed and P24 is set to a one: the OBF flag is gated onto KIRQ. The KIRQ
signal can be connected to system interrupt to signify that the LPC47B27x CPU has written to the output
data register via "OUT DBB,A". If P24 is set to a zero, KIRQ is forced low. On power-up, after a valid RST
pulse has been delivered to the device, KIRQ is reset to 0. KIRQ will normally reflects the status of writes
"DBB". (KIRQ is normally selected as IRQ1 for keyboard support.)
If "EN FLAGS” has not been executed: KIRQ can be controlled by writing to P24. Writing a zero to P24
forces KIRQ low; a high forces KIRQ high.
MIRQ
If "EN FLAGS" has been executed and P25 is set to a one:; IBF is inverted and gated onto MIRQ. The
MIRQ signal can be connected to system interrupt to signify that the LPC47B27x CPU has read the DBB
register. If "EN FLAGS” has not been executed, MIRQ is controlled by P25, Writing a zero to P25 forces
MIRQ low, a high forces MIRQ high. (MIRQ is normally selected as IRQ12 for mouse support).
Gate A20
A general purpose P21 is used as a software controlled Gate A20 or user defined output.
8042 PINS
The 8042 functions P17, P16 and P12 are implemented as in a true 8042 part. Reference the 8042 spec
for all timing. A port signal of 0 drives the output to 0. A port signal of 1 causes the port enable signal to
drive the output to 1 within 20-30nsec. After 500nsec (six 8042 clocks) the port enable goes away and the
external pull-up maintains the output signal as 1.
In 8042 mode, the pins can be programmed as open drain. When programmed in open drain mode, the
port enables do not come into play. If the port signal is 0 the output will be 0. If the port signal is 1, the
output tristates: an external pull-up can pull the pin high, and the pin can be shared. In 8042 mode, the
pins cannot be programmed as input nor inverted through the GP configuration registers.
FLAG
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