參數(shù)資料
型號(hào): LP61L256CS-15
廠商: AMIC Technology Corporation
元件分類: SRAM
英文描述: 32K X 8 BIT HIGH SPEED CMOS SRAM
中文描述: 32K的× 8位高速CMOS SRAM的
文件頁(yè)數(shù): 2/11頁(yè)
文件大?。?/td> 110K
代理商: LP61L256CS-15
Preliminary
LP61L256C
32K X 8 BIT HIGH SPEED CMOS SRAM
PRELIMINARY
(November, 2001, Version 0.0)
1
AMIC Technology, Inc.
Features
n
Single +3.3V power supply
n
Access times: 12/15 ns (max.)
n
Current: Operating: 120mA (max.)
Standby:
n
Full static operation, no clock or refreshing required
General Description
The LP61L256C is a high-speed, low-power 262,144-bit
static random access memory organized as 32,768
words by 8 bits and operates on a single 3.3V power
supply. It is built using high performance CMOS process.
Inputs and three-state outputs are TTL compatible and
allow for direct interfacing with common system bus
structures.
Pin Configurations
5mA (max.)
n
All inputs and outputs are directly TTL compatible
n
Common I/O using three-state output
n
Data retention voltage: 2V (min.)
n
Available in 28-pin SOJ package
Minimum standby power is drawn by this device when
CE is at a high level, independent of the other input
levels.
Data retention is guaranteed at a power supply voltage
as low as 2V.
n
SOJ
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O
0
I/O
1
I/O
2
GND
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
CE
OE
A11
A9
A8
A13
WE
VCC
A10
L
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
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