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參數(shù)資料
| 型號(hào)： | LM3S101 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Microcontroller |
| 中文描述： | 微控制器 |
| 文件頁(yè)數(shù)： | 39/284頁(yè) |
| 文件大?。?/td> | 1774K |
| 代理商： | LM3S101 |
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JTAG Interface
39
March 22, 2006
Preliminary
5.2.4.1
GPIO Functionality
Caution – If the JTAG pins will be used as GPIOs, it is possible to create a software sequence that
prevents the debugger from connecting to the Stellaris microcontroller. If the program code loaded
into flash immediately changes the JTAG pins to their GPIO functionality, the debugger will not
have enough time to connect and halt the controller before the JTAG pin functionality switches.
This locks the debugger out of the part. This can be avoided with a software routine that restores
JTAG functionality using an external trigger.
When the controller is reset with either a POR or
RST
, the JTAG port pins default to their JTAG
configurations. The default configuration includes enabling the pull-up resistors (setting
GPIOPUR
to 1 for
PB7
and
PC[3:0]
) and enabling the alternate hardware function (setting
GPIOAFSEL
to 1
for
PB7
and
PC[3:0]
) on the JTAG pins.
It is possible for software to configure these pins as GPIOs after reset by writing 0s to the
GPIOAFSEL
registers of
PB7
and
PC[3:0]
. If the user does not require the JTAG port for
debugging or board-level testing, this will provide five more GPIOs for use in the design.
Important:
If the JTAG pins will be used as GPIOs in a design,
PB7
and
PC2
cannot have
external pull-down resistors connected to both of them at the same time. If both pins
are pulled Low during reset, the controller will have unpredictable behavior. If this
happens, remove one or both of the pull-down resistors, and apply
RST
or power-
cycle the part.
5.2.4.2
ARM Serial Wire Debug (SWD)
In order to seamlessly integrate the ARM Serial Wire Debug (SWD) functionality, a serial-wire
debugger must be able to connect to the Cortex-M3 core without having to perform, or have any
knowledge of, JTAG cycles. This is accomplished with a SWD preamble that is issued before the
SWD session begins.
The preamble used to enable the SWD interface of the SWJ-DP module starts with the TAP
controller in the Test-Logic-Reset state. From here, the preamble sequences the TAP controller
through the following states: Run Test Idle, Select DR, Select IR, Capture IR, Exit1 IR, Update IR,
Run Test Idle, Select DR, Select IR, Capture IR, Exit1 IR, Update IR, Run Test Idle, Select DR,
Select IR, and Test-Logic-Reset states.
Stepping through the JTAG TAP Instruction Register (IR) load sequences of the TAP state
machine twice without shifting in a new instruction enables the SWD interface and disables the
JTAG interface. For more information on this operation and the SWD interface, see the
ARM
Cortex-M3 Technical Reference Manual
and the
ARM CoreSight Technical Reference Manual
.
Because this sequence is a valid series of JTAG operations that could be issued, the ARM JTAG
TAP controller is not fully compliant to the
IEEE Standard 1149.1
. This is the only instance where
the ARM JTAG TAP controller does not meet full compliance with the specification. Due to the low
probability of this sequence occuring during normal operation of the TAP controller, it should not
affect normal performance of the JTAG interface.
5.3
Register Descriptions
There are no APB-accessible registers in the JTAG TAP Controller or shift register chains. The
registers within the JTAG controller are all accessed serially through the TAP Controller. The
registers can be broken down into two main categories: Instruction Registers and Data Registers.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LM3S101_0610 | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Microcontroller |
| LM3S101-CRN20 | 功能描述:ARM微控制器 - MCU MICROCONTROLLER RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 處理器系列:STM32F373xx 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:72 MHz 程序存儲(chǔ)器大小:256 KB 數(shù)據(jù) RAM 大小:32 KB 片上 ADC:Yes 工作電源電壓:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LQFP-48 安裝風(fēng)格:SMD/SMT |
| LM3S101-CRN20-XNPP | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Microcontroller |
| LM3S101-CRN20-XNPR | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Microcontroller |
| LM3S101-CRN20-XNPT | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Microcontroller |
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