
General-Purpose Timers
133
March 22, 2006
Preliminary
The
32KHZ
pin is dedicated to the 32-bit RTC function, and the input clock is 32 KHz.
When software writes the
TAEN
bit in
GPTMCTL
, the counter starts counting up from its preloaded
value of 0x00000001. When the current count value matches the preloaded value in
GPTMTAMATCHR
, it rolls over to a value of 0x00000000 and continues counting until either a
hardware reset, or it is disabled by software (clearing the
TAEN
bit). When a match occurs, the
GPTM asserts the
RTCRIS
bit in
GPTMRIS
. If the RTC interrupt is enabled in
GPTIMR
, the GPTM
also sets the
RTCMIS
bit in
GPTMISR
and generates a controller interrupt. The status flags are
cleared by writing the
RTCCINT
bit in
GPTMICR
.
If the
TASTALL
and/or
TBSTALL
bits in the
GPTMCTL
register are set, the timer does not freeze if
the
RTCEN
bit is set in
GPTMCTL
.
9.2.3
16-Bit Timer Operating Modes
The GPTM is placed into global 16-bit mode by writing a value of 0x4 to the
GPTM Configuration
(GPTMCFG)
register (see page 141). This section describes each of the GPTM 16-bit modes of
operation. Timer A and Timer B have identical modes, so a single description is given using an
n
to
reference both.
9.2.3.1
16-Bit One-Shot/Periodic Timer Mode
In 16-bit one-shot and periodic timer modes, the timer is configured as a 16-bit down-counter with
an optional 8-bit prescaler that effectively extends the counting range of the timer to 24 bits. The
selection of one-shot or periodic mode is determined by the value written to the
TnMR
field of the
GPTMTnMR
register. The optional prescaler is loaded into the
Timern Prescale (GPTMTnPR)
register.
When software writes the
TnEN
bit in the
GPTMCTL
register, the timer begins counting down from
its preloaded value. Once the 0x0000 state is reached, the timer reloads its start value from
GPTMTnILR
and
GPTMTnPR
on the next cycle. If configured to be a one-shot timer, the timer
stops counting and clears the
TnEN
bit in the
GPTMCTL
register. If configured as a periodic timer,
it continues counting.
In addition to reloading the count value, the timer generates interrupts and output triggers when it
reaches the 0x0000 state. The GPTM sets the
TnTORIS
bit in the
GPTMRIS
register, and holds it
until it is cleared by writing the
GPTMICR
register. If the time-out interrupt is enabled in
GPTIMR
,
the GPTM also sets the
TnTOMIS
bit in
GPTMISR
and generates a controller interrupt.
The output trigger is a one-clock-cycle pulse that is asserted when the counter hits the 0x0000
state, and deasserted on the following clock cycle. It is enabled by setting the
TnOTE
bit in the
GPTMCTL
register, and can trigger SoC-level events.
If software reloads the
GPTMTAILR
register while the counter is running, the counter loads the
new value on the next clock cycle and continues counting from the new value.
If the
TnSTALL
bit in the
GPTMCTL
register is enabled, the timer freezes counting until the signal
is deasserted.
The following example shows a variety of configurations for a 16-bit free running timer while using
the prescaler. All values assume a 50 MHz clock with Tc=20 ns (clock period).
Table 9-1.
16-Bit Timer With Prescaler Configurations
Prescale
#Clock (T
c
)
a
Max Time
Units
00000000
1
1.3107
mS
00000001
2
2.6214
mS