參數資料
型號: LM25066PSQ
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 電源管理
英文描述: POWER SUPPLY SUPPORT CKT, QCC24
封裝: LLP-24
文件頁數: 39/48頁
文件大?。?/td> 1456K
代理商: LM25066PSQ
SMBus Communications Timing
Requirements
301158a1
FIGURE 19. SMBus Timing Diagram
TABLE 45. SMBus Timing Definition
Symbol
Parameter
Limits
Units
Comments
Min
Max
F
SMB
SMBus Operating Frequency
10
400
kHz
T
BUF
Bus free time between Stop and Start Condition
1.3
s
T
HD:STA
Hold time after (Repeated) Start Condition. After this
period, the first clock is generated.
0.6
s
T
SU:STA
Repeated Start Condition setup time
0.6
s
T
SU:STO
Stop Condition setup time
0.6
s
T
HD:DAT
Data hold time
300
ns
T
SU:DAT
Data setup time
100
ns
T
TIMEOUT
Clock low time-out
25
35
ms
T
LOW
Clock low period
1.5
s
T
HIGH
Clock high period
0.6
s
T
LOW:SEXT
Cumulative clock low extend time (slave device)
25
ms
T
LOW:MEXT
Cumulative low extend time (master device)
10
ms
T
F
Clock or Data Fall Time
20
300
ns
T
R
Clock or Data Rise Time
20
300
ns
Note 8:
Devices participating in a transfer will timeout when any clock low exceeds the value of T
TIMEOUT,MIN of 25 ms. Devices that have detected a timeout
condition must reset the communication no later than T
TIMEOUT,MAX of 35 ms. The maximum value must be adhered to by both a master and a slave as it incorporates
the cumulative stretch limit for both a master (10ms) and a slave (25ms).
Note 9:
T
HIGH MAX provides a simple method for devices to detect bus idle conditions.
Note 10:
T
LOW:SEXT is the cumulative time a slave device is allowed to extend the clock cycles in one message from the initial start to the stop. If a slave exceeds
this time, it is expected to release both its clock and data lines and reset itself.
Note 11:
T
LOW:MEXT is the cumulative time a master device is allowed to extend its clock cycles within each byte of a message as defined from start-to-ack, ack-
to-ack, or ack-to-stop.
Note 12:
Rise and fall time is defined as follows:
T
R = ( VILMAX – 0.15) to (VIHMIN + 0.15)
T
F = 0.9 VDD to (VILMAX – 0.15)
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LM25066
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