參數(shù)資料
型號(hào)： LM1246NA
廠商： National Semiconductor Corporation
英文描述： 150 MHz I2C Compatible RGB Preamplifier with Internal 512 Character OSD ROM, 512 Character RAM and 4 DACs
中文描述： 150 MHz的I2C兼容的RGB前置放大器512個(gè)字符OSD光盤，512個(gè)字符RAM和4 DAC的內(nèi)置
文件頁(yè)數(shù)： 10/51頁(yè)
文件大小： 2794K
代理商： LM1246NA
Typical Performance Characteristics
V
CC
= 5V, T
A
= 25C unless otherwise specified (Continued)
TABLE 3. OSD Register Recommendations
PPL=0
25 - 110
PPL=1
25 - 110
PPL=2
25 - 110
PPL=3
25 - 110
PPL=4
25 - 110
PPL=5
25 - 108
PPL=6
25 - 102
PPL=7
25 - 96
PLL Auto
If 1152 pixels per line is being used, the horizontal scan rate
would have to be lower than 106 kHz in order to not exceed
the maximum OSD pixel frequency of 111 MHz. The maxi-
mum number of vertical video lines that may be used is 1536
lines as in a 2048x1536 display. The LM1246 has a
PLL
Auto
feature, which will automatically select an internal PLL
frequency range setting that will guarantee optimal OSD
locking for any horizontal scan rate. This offers improved
PLL performance and eliminates the need for PLL register
settings determined by the user. To initialize the PLL Auto
feature, set bits, 0x843E[1:0] to 0 for pre-calibration, which
takes one vertical scan period to complete, and must be
done while the video is blanked. Subsequently, set
0x843E[6] to 1, which must also be done while the video is
blanked.
Table 3. OSD Register Recommendations
shows
the recommended horizontal scan rate ranges (in kHz) for
each pixels per line register setting, 0x8401[7:5]. These
ranges are recommended for chip ambient temperatures of
0
o
C to 70
o
C, and the recommended PLL filter values are
6.2kohms, 0.01uF, and 1000pF as shown in the schematic.
While the OSD PLL will lock for other register combinations
Pin Descriptions and Application Information
and at scan rates outside these ranges, the performance of
the loop will be improved if these recommendations are
followed.
PLL Auto Mode Initialization Sequence
Blank video
In PLL manual mode, set PLL range (0x843E[1:0]) to 0
Wait for at least one vertical period or vertical sync pulse
to pass
Set 0x843E[6] to 1 to activate the Auto mode
Wait for at least one vertical period or vertical sync pulse
to pass
Unblank video
This Sequence must be done by the microcontroller at sys-
tem power up, as well as each time there is a horizontal line
rate change from the video source, for the PLLAuto mode to
function properly.
Pin
No.
1
Pin Name
Schematic
Description
V Flyback
Required for OSD synchronization and is also
used for vertical blanking of the video outputs.
The actual switching threshold is about 35% of
V
CC
. For logic level inputs C
4
can be a jumper,
but for flyback inputs, an AC coupled
differentiator is recommended, where R
V
is large
enough to prevent the voltage at pin 1 from
exceeding V
CC
or going below GND. C
4
should
be small enough to flatten the vertical rate ramp
at pin 1. C
24
may be needed to reduce noise.
Provides filtering for the internal voltage which
sets the internal bias current in conjunction with
R
EXT
. A minimum of 0.1 μF is recommended for
proper filtering. This capacitor should be placed
as close to pin 2 and the pin 4 ground return as
possible.
2
V
REF
Bypass
L
www.national.com
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LM1247 制造商:NSC 制造商全稱:National Semiconductor 功能描述:150 MHz I2C Compatible RGB Preamplifier with Internal 512 Character OSD ROM, 512 Character RAM and 4 DACs
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