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參數(shù)資料
| 型號： | LC866524 |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 英文描述： | 8-Bit Single Chip Microcontroller with the UVEPROM |
| 中文描述： | 8位單片機(jī)微控制器與UVEPROM |
| 文件頁數(shù)： | 14/21頁 |
| 文件大小： | 631K |
| 代理商： | LC866524 |
LC86E6548
No.6747-14/21
Ratings
typ.
Parameter
Symbol
Pins
Conditions
VDD[V]
4.5 to 6.0
min.
-1
max.
unit
IOFF(1)
Output P-channel
Tr. OFF
VOUT=VSS
Output P-channel
Tr. OFF
VOUT=VDD-40V
Output P-channel
Tr. OFF
Using as input ports
Output P-channel
Tr. OFF
VOUT=3V
Vp=-30V
VSS=GND
Vp=-30V
Output disable
Output off-
leakage current
IOFF(2)
S0/T0 to S6/T6
S32 to S51
(without pull-down
resistor)
4.5 to 6.0
-30
μ
A
Resistance of
The low level
Hold Tr.
High voltage
Pull-down
resistor
Rinpd
S16 to S51
4.5 to 6.0
200
Rpd
S7/T7 to S15/T15
S16 to S31
5.0
60
100
200
VP pull-down
resistor
Hysteresis
voltage
Rvppd
Vp
5.0
60
100
200
k
VHIS
Port 1
Ports 70,71,72,73,75
RES
All pins
4.5 to 6.0
0.1VDD
V
Pin capacitance
CP
f=1MHz
VIN=VSS for all
unmeasured terminals.
Ta=25
°
C
4.5 to 6.0
10
pF
4. Serial Input / Output Characteristics at Ta=+10
°
C to +40
°
C, VSS1=VSS2=0V
Ratings
typ.
Parameter
Symbol
Pins
Conditions
VDD[V]
4.5 to 6.0
min.
2
1
max.
unit
Cycle
Low Level
pulse width
High Level
pulse width
Cycle
Low Level
pulse width
High Level
pulse width
Data set-up time
Data hold time
Output delay time
(External clock
using for serial
transfer clock)
Output delay time
(Internal clock
using for serial
transfer clock)
tCKCY(1)
tCKL(1)
I
tCKH(1)
SCK0,SCK1
Refer to figure 5
1
tCKCY(2)
tCKL(2)
2
1/2tCKCY
S
O
tCKH(2)
SCK0,SCK1
Use pull-up
resistor (1k
) in
the open drain
output.
Refer to figure 5
Data set-up to
SCK0,1
Data hold from
SCK0,1
Refer to figure 5
Use pull-up
resistor (1k
) in
the open drain
output.
Data hold from
SCK0,1
Refer to figure 5
4.5 to 6.0
1/2tCKCY
tCYC
tICK
0.1
S
tCKI
SI0,SI1
SB0,SB1
4.5 to 6.0
0.1
tCKO(1)
7/12
tCYC
+0.2
S
tCKO(2)
SO0,SO1
SB0,SB1
4.5 to 6.0
1/3
tCYC
+0.2
μ
s
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