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No. 5919-26/35
LC74775, 74775M
DA 0 to 7
Register
Contents
Notes
State
Function
7
–
1
6
–
1
Command 7 identification code.
5
–
1
Display control setup.
4
–
1
3
–
1
2
–
0
Extended command 8 identification code
1
–
0
–
0
First byte
COMMAND16 (VPS/PDC control setup command) I2C bus only
DA 0 to 7
Register
Contents
Notes
State
Function
7
–
0
Second byte identification bit
0
Byte 19 Hamming error check on (Data hold)
6
ECP19
{Bytes 44, 28, 36, 20, 32, 42, 32, and 42}
1
Byte 19 Hamming error check off (Data write)
{Bytes 44, 28, 36, 20, 32, 42, 32, and 42}
0
Byte 18 Hamming error check on (Data hold)
5
ECP18
{Bytes 43, 27, 35, 19, 31, 41, 31, and 41}
1
Byte 18 Hamming error check off (Data write)
{Bytes 43, 27, 35, 19, 31, 41, 31, and 41}
0
Byte 17 Hamming error check on (Data hold)
4
ECP17
{Bytes 42, 26, 34, 18, 30, 40, 30, and 40}
1
Byte 17 Hamming error check off (Data write)
{Bytes 42, 26, 34, 18, 30, 40, 30, and 40}
0
Byte 16 Hamming error check on (Data hold)
3
ECP16
{Bytes 41, 25, 33, 17, 29, 39, 29, and 39}
1
Byte 16 Hamming error check off (Data write)
{Bytes 41, 25, 33, 17, 29, 39, 29, and 39}
0
Byte 15 Hamming error check on (Data hold)
2
ECP15
{Bytes 40, 24, 32, 16, 28, 38, 28, and 38}
1
Byte 15 Hamming error check off (Data write)
{Bytes 40, 24, 32, 16, 28, 38, 28, and 38}
0
Byte 14 Hamming error check on (Data hold)
1
ECP14
{Bytes 39, 23, 31, 15, 27, 37, 27, and 37}
1
Byte 14 Hamming error check off (Data write)
{Bytes 39, 23, 31, 15, 27, 37, 27, and 37}
0
Byte 13 Hamming error check on (Data hold)
0
ECP13
{Bytes 38, 22, 30, 14, 26, 36, 26, and 36}
1
Byte 13 Hamming error check off (Data write)
{Bytes 38, 22, 30, 14, 26, 36, 26, and 36}
Second byte
Note: All registers are set to 0 when the LC74775/M is reset by the RST pin.
Specification when the PDC data BMS bit is 0.
The item in parentheses is the specification
when the BMS bit is 1.
The item in curly braces lists the odd parity
check on/off bytes for header modes 1, 2, 3,
and 4 and status mode 1, 2, 3, and 4.