參數資料
型號: LC74775
元件分類: 畫面疊加
英文描述: ON-SCREEN DISPLAY IC, PDIP30
封裝: SDIP-30
文件頁數: 20/35頁
文件大?。?/td> 258K
代理商: LC74775
No. 5919-27/35
LC74775, 74775M
DA 0 to 7
Register
Contents
Notes
State
Function
7
1
6
1
Command 7 identification code.
5
1
Display control setup.
4
1
3
1
2
0
Extended command 9 identification code
1
0
1
First byte
COMMAND17 (VPS/PDC control setup command) I2C bus only
DA 0 to 7
Register
Contents
Notes
State
Function
7
0
Second byte identification bit
6
0
Byte 25 Hamming error check on (Data hold)
5
ECP25
1
Byte 25 Hamming error check off (Data write)
0
Byte 24 Hamming error check on (Data hold)
4
ECP24
1
Byte 24 Hamming error check off (Data write)
0
Byte 23 Hamming error check on (Data hold)
3
ECP23
1
Byte 23 Hamming error check off (Data write)
0
Byte 22 Hamming error check on (Data hold)
2
ECP22
{Bytes , , , , 35, 45, 35, and 45}
1
Byte 22 Hamming error check off (Data write)
{Bytes , , , , 35, 45, 35, and 45}
0
Byte 21 Hamming error check on (Data hold)
1
ECP21
{Bytes , , , , 34, 44, 34, and 44}
1
Byte 21 Hamming error check off (Data write)
{Bytes , , , , 34, 44, 34, and 44}
0
Byte 20 Hamming error check on (Data hold)
0
ECP20
{Bytes 45, 29, 37, 21, 33, 43, 33, and 43}
1
Byte 20 Hamming error check off (Data write)
{Bytes 45, 29, 37, 21, 33, 43, 33, and 43}
Second byte
Note: All registers are set to 0 when the LC74775/M is reset by the RST pin.
Specification when the PDC data BMS bit is 0.
The item in parentheses is the specification
when the BMS bit is 1.
The item in curly braces lists the odd parity
check on/off bytes for header modes 1, 2, 3,
and 4 and status mode 1, 2, 3, and 4.
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