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Address/data write timing
Data read timing
2. Serial interface
The serial interface uses the following three input pins and one output pin.
CE pin (pin 43: input): Serial transfer enable signal input
CL pin (pin 44: input): Serial transfer clock signal input
DO pin (pin 45: input): Serial transfer data output
DI pin (pin 46: input) Serial data input
Data transfer is active while the CE pin is high level.
Data transfer proceeds in LSB to first order.
Data input is synchronized with the rising edge of the clock.
Data output is synchronized with the falling edge of the clock.
Notes: Do not write command or other data to the serial data input pin while the LSI is writing data. The serial data
output pin is in the high impedance state during data input.
2-1 Address and data transfer procedures
The command address is assigned to the lowest seven bits of the address. The most significant bit (AD7) is used to
specify write or read. The address can only be written. It cannot be read.
Data transfer proceeds in LSB to first order.
Address input and data I/O are valid while the CE pin (pin 43) is high level.
Supply the serial data input clock to the CL pin (pin 44). The LSI reads and writes data in synchronization with the
rising edge of the serial clock signal.
No. 5684-17/21
LC74201E