參數(shù)資料
型號: L6740L
廠商: STMICROELECTRONICS
元件分類: 模擬信號調(diào)理
英文描述: SPECIALTY ANALOG CIRCUIT, PQFP48
封裝: 7 X 7 MM, 1 MM HEIGHT, HTQFP-48
文件頁數(shù): 19/44頁
文件大?。?/td> 755K
代理商: L6740L
Output voltage positioning
L6740L
this case, simply connect a resistor RLI to SGND: the resulting voltage drop across RLI will
be proportional to the delivered current according to the following relationship:
In case no additional information about the delivered current is requested, the DROOP pin
can be shorted to SGND.
Note:
Split between RFB_COMP and RFB_DROOP (Figure 9) is useful in custom designs where the
Droop effect is minimum (i.e. <50mV over 100A) to simplify the compensation network
design.
6.4
CORE section - offset (optional)
The OS pin allows programming a positive offset (VOS) for the CORE section output voltage
by connecting a resistor ROS to SGND. The pin is internally fixed at 1.240 V so a current is
programmed by connecting the resistor ROS between the pin and SGND: this current is mir-
rored and then properly sunk from the FB pin as shown in Figure 9. Output voltage is then
programmed as follow:
Offset resistor can be designed by considering the following relationship (RFB is be fixed by
the Droop effect):
Caution:
Offset implementation is optional, in case it is not desired, simply short the pin to SGND.
Note:
In the above formulas, RFB has to be considered being the total resistance connected
between FB pin and the regulated voltage.
6.5
NB section - current reading
L6740L embeds a flexible, fully-differential current sense circuitry for the NB section that is
able to read across low-side MOSFET RDS(on) or across a sense resistor placed in series to
the element. The trans-conductance ratio is issued by the external resistor RISEN placed
outside the chip between NB_ISEN pin and the low-side drain. The current sense circuit
performs sample and hold of the current information. The current that flows from the
NB_ISEN pin is then given by the following equation (See Figure 10):
RISEN resistor is typically designed according to the OC Threshold. See Section 7.4 for
details.
V
DROOP
R
LI
DCR
R
G
------------- I
OUT
=
V
CORE
VID
R
FB
I
DROOP
I
OS
()
=
R
OS
1.240V
V
OS
------------------- R
FB
=
I
ISEN
R
dsON
R
ISEN
----------------- I
NB
I
DROOP_NB
==
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