參數(shù)資料
型號(hào)： KSZ8862-16MQL-FX
廠商： Micrel Inc
文件頁(yè)數(shù)： 93/125頁(yè)
文件大?。?/td> 0K
描述： IC SWITCH ETH 2P 16BIT 128PQFP
標(biāo)準(zhǔn)包裝： 66
系列： KSZ8862
控制器類型： 以太網(wǎng)開(kāi)關(guān)控制器
接口： PCI
安裝類型： 表面貼裝
封裝/外殼： 128-BFQFP
供應(yīng)商設(shè)備封裝： 128-PQFP（14x20）
包裝： 托盤
產(chǎn)品目錄頁(yè)面： 1081 (CN2011-ZH PDF)
配用： 576-1638-ND - BOARD EVALUATION KSZ8862-10FL
576-1637-ND - BOARD EVALUATION KSZ8862-100FX
其它名稱： 576-3271
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Micrel, Inc.
KSZ8862-16/32MQL
April 2007
7
M9999-040407-3.0
Bank 45 PHY 1 MII-Register Basic Status Register (0x02): P1MBSR...........................................................................82
Bank 45 PHY 1 PHYID Low Register (0x04): PHY1ILR.................................................................................................82
Bank 45 PHY 1 PHYID High Register (0x06): PHY1IHR ...............................................................................................82
Bank 45 PHY 1 Auto-Negotiation Advertisement Register (0x08): P1ANAR.................................................................83
Bank 45 PHY 1 Auto-Negotiation Link Partner Ability Register (0x0A): P1ANLPR .......................................................83
Bank 46 PHY 2 MII-Register Basic Control Register (0x00): P2MBCR .........................................................................84
Bank 46 PHY 2 MII-Register Basic Status Register (0x02): P2MBSR...........................................................................85
Bank 46 PHY 2 PHYID Low Register (0x04): PHY2ILR.................................................................................................85
Bank 46 PHY 2 PHYID High Register (0x06): PHY2IHR ...............................................................................................85
Bank 46 PHY 2 Auto-Negotiation Advertisement Register (0x08): P2ANAR.................................................................86
Bank 46 PHY 2 Auto-Negotiation Link Partner Ability Register (0x0A): P2ANLPR .......................................................86
Bank 47 PHY1 Special Control/Status Register (0x02): P1PHYCTRL ..........................................................................87
Bank 47 PHY2 LinkMD
Control/Status (0x04): P2VCT ................................................................................................87
Bank 47 PHY2 Special Control/Status Register (0x06): P2PHYCTRL ..........................................................................88
Bank 48 Port 1 Control Register 1 (0x00): P1CR1 .........................................................................................................88
Bank 48 Port 1 Control Register 2 (0x02): P1CR2 .........................................................................................................89
Bank 48 Port 1 VID Control Register (0x04): P1VIDCR.................................................................................................90
Bank 48 Port 1 Control Register 3 (0x06): P1CR3 .........................................................................................................90
Bank 48 Port 1 Ingress Rate Control Register (0x08): P1IRCR.....................................................................................91
Bank 48 Port 1 Egress Rate Control Register (0x0A): P1ERCR....................................................................................93
Bank 49 Port 1 PHY Special Control/Status, LinkMD
(0x00): P1SCSLMD..................................................................95
Bank 49 Port 1 Control Register 4 (0x02): P1CR4 .........................................................................................................95
Bank 49 Port 1 Status Register (0x04): P1SR................................................................................................................96
Bank 50 Port 2 Control Register 1 (0x00): P2CR1 .........................................................................................................97
Bank 50 Port 2 Control Register 2 (0x02): P2CR2 .........................................................................................................97
Bank 50 Port 2 VID Control Register (0x04): P2VIDCR.................................................................................................97
Bank 50 Port 2 Control Register 3 (0x06): P2CR3 .........................................................................................................97
Bank 50 Port 2 Ingress Rate Control Register (0x08): P2IRCR.....................................................................................97
Bank 50 Port 2 Egress Rate Control Register (0x0A): P2ERCR....................................................................................97
Bank 51 Port 2 PHY Special Control/Status, LinkMD
(0x00): P2SCSLMD..................................................................98
Bank 51 Port 2 Control Register 4 (0x02): P2CR4 .........................................................................................................99
Bank 51 Port 2 Status Register (0x04): P2SR..............................................................................................................100
Bank 52 Host Port Control Register 1 (0x00): P3CR1 .................................................................................................101
Bank 52 Host Port Control Register 2 (0x02): P3CR2 .................................................................................................101
Bank 52 Host Port VID Control Register (0x04): P3VIDCR .........................................................................................102
Bank 52 Host Port Control Register 3 (0x06): P3CR3 .................................................................................................102
Bank 52 Host Port Ingress Rate Control Register (0x08): P3IRCR .............................................................................102
Bank 52 Host Port Egress Rate Control Register (0x0A): P3ERCR ............................................................................102
Banks 53 – 63: Reserved .............................................................................................................................................102
MIB (Management Information Base) Counters...........................................................................................................103
Format of “All Ports Dropped Packet” MIB Counters ...................................................................................................104
Additional MIB Information............................................................................................................................................105
Static MAC Address Table .............................................................................................................................................106
Static MAC Table Lookup Examples: ...........................................................................................................................106
Dynamic MAC Address Table ........................................................................................................................................107
Dynamic MAC Address Lookup Example:....................................................................................................................107
VLAN Table ......................................................................................................................................................................108
VLAN Table Lookup Examples:....................................................................................................................................108
Absolute Maximum Ratings
(1) ........................................................................................................................................109
Operating Ratings
(1) ........................................................................................................................................................109
Electrical Characteristics
(1) ............................................................................................................................................110
Timing Specifications .....................................................................................................................................................111
Asynchronous Timing without using Address Strobe (ADSN = 0) ...............................................................................111
Asynchronous Timing Using Address Strobe (ADSN) .................................................................................................112
Asynchronous Timing Using DATACSN.......................................................................................................................113
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