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參數(shù)資料
| 型號： | KSZ8862-16MQL-FX |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 56/125頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SWITCH ETH 2P 16BIT 128PQFP |
| 標準包裝： | 66 |
| 系列： | KSZ8862 |
| 控制器類型： | 以太網(wǎng)開關控制器 |
| 接口： | PCI |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 128-BFQFP |
| 供應商設備封裝： | 128-PQFP（14x20） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 1081 (CN2011-ZH PDF) |
| 配用： | 576-1638-ND - BOARD EVALUATION KSZ8862-10FL 576-1637-ND - BOARD EVALUATION KSZ8862-100FX |
| 其它名稱： | 576-3271 |
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Micrel, Inc.
KSZ8862-16/32MQL
April 2007
36
M9999-040407-3.0
Synchronous Interface
For synchronous transfers, the synchronous dedicated signals CYCLEN, SWR, and RDYRTNN will toggle but the
asynchronous dedicated signals RDN and WRN are de-asserted and stay at the same logic level throughout the entire
synchronous transfer.
The synchronous interface mainly supports two applications, one for VLBus-like and the other for EISA-like (DMA type C)
burst transfers. The VLBus-like interface supports only single-data transfer. The pin option VLBUSN determines if it is a
VLBus-like or EISA-like burst transfer – if VLBUSN = 0, the interface is for VLBus-like transfer; if VLBUSN = 1, the
interface is for EISA-like burst transfer.
For VLBus-like transfer interface (VLBUSN = 0):
This interface is used in an architecture in which the device’s local decoder is utilized; that is, the BIU decodes latched
A[15:4] and qualifies with AEN (Address Enable) to determine if the switch is the intended target. No burst is
supported in this application. The M/nIO signal connection in VLBus is routed to AEN. The CYCLEN in this application
is used to sample the SWR signal when it is asserted. Usually, CYCLEN is one clock delay of ADSN. There is a
handshaking process to end the cycle of VLBus-like transfers. When the KSZ8862M is ready to finish the cycle, it
asserts SRDYN
. The system/host acknowledges SRDYN by asserting RDYRTNN after the system/host has latched
the read data. The KSZ8862M holds the read data until RDYRTNN is asserted. The timing waveform is shown in
Figure 22 and Figure 23.
For EISA-like burst transfer interface (VLBUSN = 1):
The SWR is connected to IORC# in EISA to indicate the burst read and CYCLEN is connected to IOWC# in EISA to
indicate the burst write. Note that in this application, both the system/host/memory and KSZ8862M are capable of
inserting wait states. For system/host/memory to insert a wait state, assert the RDYRTNN signal; for the KSZ8862M
to insert the wait state, assert the SRDYN signal. The timing waveform is shown in Figure 20 and Figure 21.
Summary
Figure 9 shows the mapping from ISA-like, EISA-like and VLBus-like transactions to the switch’s BIU.
Figure 10 shows the connection for different data bus sizes.
Note: For the 8-bit data bus mode, the internal inverter is enabled and connected between BE0N and BE1N, so even
address will enable the BE0N and odd address will enable the BE1N.
KSZ8862M BIU
Asynchronous
Interface
Synchronous
Interface
Address Latch
No Addr Latch
(ADSN = 0)
Central decode
Local
decode
Address Latch
Central decode
(VLBUSN = 1)
Local
decode
(VLBUSN = 0)
Host Logic
ISA
EISA
VLBus
Burst
Non-burst
Note: To use DATACSN & 32-bit only for Central decode
Figure 9. Mapping from ISA-like, EISA-like, and VLBus-like transactions to the KSZ8862M Bus
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