參數(shù)資料
型號(hào): KSZ8862-16MQL-FX
廠商: Micrel Inc
文件頁數(shù): 5/125頁
文件大?。?/td> 0K
描述: IC SWITCH ETH 2P 16BIT 128PQFP
標(biāo)準(zhǔn)包裝: 66
系列: KSZ8862
控制器類型: 以太網(wǎng)開關(guān)控制器
接口: PCI
安裝類型: 表面貼裝
封裝/外殼: 128-BFQFP
供應(yīng)商設(shè)備封裝: 128-PQFP(14x20)
包裝: 托盤
產(chǎn)品目錄頁面: 1081 (CN2011-ZH PDF)
配用: 576-1638-ND - BOARD EVALUATION KSZ8862-10FL
576-1637-ND - BOARD EVALUATION KSZ8862-100FX
其它名稱: 576-3271
Micrel, Inc.
KSZ8862-16/32MQL
April 2007
102
M9999-040407-3.0
Bit
Default
R/W
Description
register, replace the packet’s “user priority field” with the “user priority field” in the port default tag
register.
0 = do no compare and replace the packet’s ‘user priority field.”
2-0
0x7
RW
Port VLAN Membership
Define the port’s Port VLAN membership. Bit 2 stands for host port, bit 1 for port 2, and bit 0 for port
1. The port can only communicate within the membership. A ‘1’ includes a port in the membership; a
‘0’ excludes a port from the membership.
Bank 52 Host Port VID Control Register (0x04): P3VIDCR
This register contains the global per port control for the switch function. See description in P1VIDCR, Bank 48 (0x04)
Bank 52 Host Port Control Register 3 (0x06): P3CR3
This register contains the global per port control for the switch function. See description in P1CR3, Bank 48 (0x06)
Bank 52 Host Port Ingress Rate Control Register (0x08): P3IRCR
This register contains per port ingress rate control. See description in P1IRCR, Bank 48 (0x08)
Bank 52 Host Port Egress Rate Control Register (0x0A): P3ERCR
This register contains per port egress rate control. See description in P1ERCR, Bank 48 (0x0A)
Banks 53 – 63: Reserved
Except Bank Select Register (0xE)
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