參數(shù)資料
型號(hào): KSZ8841-16MBLI
廠商: Micrel Inc
文件頁(yè)數(shù): 39/105頁(yè)
文件大?。?/td> 0K
描述: IC MAC CTRLR 8/16BIT 100-LBGA
標(biāo)準(zhǔn)包裝: 260
控制器類(lèi)型: 以太網(wǎng)控制器,MAC
接口: 總線
電源電壓: 3.1 V ~ 3.5 V
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 100-LBGA
供應(yīng)商設(shè)備封裝: 100-LFBGA
包裝: 散裝
Micrel, Inc.
KSZ8841-16/32 MQL/MVL/MBL
October 2007
39
M9999-102207-1.6
The transmit Byte Count specifies the total number of bytes to be transmitted from the TXQ. Its format is given in Table 5.
Bit
Description
15-11
Reserved.
10-0
TXBC Transmit Byte Count
Transmit Byte Count. Hardware uses the byte count information to conserve the TX buffer
memory for better utilization of the packet memory.
Note: The hardware behavior is unknown if an incorrect byte count information is written to this
field. Writing a 0 value to this field is not permitted.
Table 5. Transmit Byte Count Format
The data area contains six bytes of Destination Address (DA) followed by six bytes of Source Address (SA), followed by a
variable-length number of bytes. On transmit, all bytes are provided by the CPU, including the source address. The
KSZ8841M does not insert its own SA. The 802.3 Frame Length word (Frame Type in Ethernet) is not interpreted by the
KSZ8841M. It is treated transparently as data both for transmit operations.
Receive Queue (RXQ) Frame Format
The frame format for the receive queue is shown in Table 6. The first word contains the status information for the frame
received. The second word is the total number of bytes of the RX frame. Following that is the packet data area. The
packet data area holds the frame itself. It may or may not include the CRC checksum depending on whether hardware
CRC stripping is enabled.
Packet Memory
Address Offset
Bit 15
Bit 0
2
nd Byte
1
st Byte
0
Status Word
2
Byte Count
4 - up
Receive Packet Data
(maximum size is 1916)
Table 6. Frame Format for Receive Queue
For receive, the packet receive status always reflects the receive status of the packet received in the current RX packet
memory (see Table 7). The RXSR register indicates the status of the current received frame.
Bit
Description
15
RXFV Receive Frame Valid
When set, this field indicates that the present frame in the receive packet memory is valid. The status
information currently in this location is also valid.
When clear, it indicates that there is either no pending receive frame or that the current frame is still
in the process of receiving.
14-8
Reserved.
7
RXBF Receive Broadcast Frame
When set, it indicates that this frame has a broadcast address.
6
RXMF Receive Multicast Frame
When set, it indicates that this frame has a multicast address (including the broadcast address).
5
RXUF Receive Unicast Frame
When set, it indicates that this frame has a unicast address.
4
Reserved.
3
RXFT Receive Frame Type
When set, it indicates that the frame is an Ethernet-type frame (frame length is greater than 1500
bytes). When clear, it indicates that the frame is an IEEE 802.3 frame.
This bit is not valid for runt frames.
2
RXTL Receive Frame Too Long
When set, it indicates that the frame length exceeds the maximum size of 1518 bytes. Frames that
are too long are passed to the host only if the pass bad frame bit is set.
Note: Frame too long is only a frame length indication and does not cause any frame truncation.
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