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參數(shù)資料
| 型號(hào)： | KMM5362205C2W |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 2M x 36 DRAM SIMM using 1Mx16 and 4M Quad CAS EDO, 1K Refresh |
| 中文描述： | 200萬× 36的DRAM上海藥物研究所和4M使用1Mx16四中科院江戶，一千刷新 |
| 文件頁數(shù)： | 7/17頁 |
| 文件大?。?/td> | 296K |
| 代理商： | KMM5362205C2W |
DRAM MODULE
KMM5362205C2W/C2WG
Rev. 0.0 (Nov. 1997)
- 7 -
NOTES
An initial pause of 200us is required after power-up followed
by any 8 RAS-only or CAS-before-RAS refresh cycles before
proper device operation is achieved.
V
IH
(min) and V
IL
(max) are reference levels for measuring
timing of input signals. Transition times are measured
between V
IH
(min) and V
IL
(max) and are assumed to be 5ns
for all inputs.
Measured with a load equivalent to 2 TTL loads and 100pF.
Operation within the
t
RCD
(max) limit insures that
t
RAC
(max)
can be met.
t
RCD
(max) is specified as a reference point only.
If
t
RCD
is greater than the specified
t
RCD
(max) limit, then
access time is controlled exclusively by
t
CAC
.
Assumes that
t
RCD
≥
t
RCD
(max).
This parameter defines the time at which the output achieves
the open circuit condition and is not referenced to V
OH
or
V
OL
.
t
WCS
is non-restrictive operating parameter. It is included in
the data sheet as electrical characteristic s only. If
t
WCS
≥
t
WCS
(min), the cycle is an early write cycle and the data
out pin will remain high impedance for the duration of the
cycle.
Either
t
RCH
or
t
RRH
must be satisfied for a read cycle.
These parameters are referenced to the CAS leading edge in
early write cycles and to the W leading edge in read-write
cycles.
Operation within the
t
RAD
(max) limit insures that
t
RAC
(max)
can be met.
t
RAD(
max) is specified as reference point only. If
t
RAD
is greater than the specified
t
RAD
(max) limit, then
access time is controlled by
t
AA
.
t
CEZ
(max),
t
REZ
(max),
t
WEZ
(max) and
t
OEZ
(max) define the
time at which the output achieves the open circuit condition
and are not referenced to output voltage level.
If RAS goes to high before CAS high going, the open circuit
condtion of the output is achieved by CAS high going. If CAS
goes to high before RAS high going, the open circuit condtion
of the output is achieved by RAS high going.
t
ASC
≥
t
CP
min
In order to hold the address latched by the first CAS going
low, the parameter
t
CLCH
must be met.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
Test condition : V
ih
/V
il
=2.4/0.8V, V
oh
/V
ol
=2.0/0.8V, Output loading CL=100pF
Parameter
Symbol
-5
-6
Unit
Note
Min
25
8
50
30
10
10
5
3
3
15
5
5
Max
Min
30
10
60
35
10
10
5
3
3
15
5
5
Max
Hyper page mode cycle time
CAS precharge time(Hyper page cycle)
RAS pulse width(Hyper page cycle)
RAS hold time from CAS precharge
W to RAS precharge time(C-B-R refresh)
W to RAS hold time(C-B-R refresh)
Output data hold time
Output buffer turn off delay from RAS
Output buffer turn off delay from W
W to data delay
W pulse width (Hyper Page Cycle)
Hold time CAS low to CAS high
t
HPC
t
CP
t
RASP
t
RHCP
t
WRP
t
WRH
t
DOH
t
REZ
t
WEZ
t
WED
t
WPE
t
CLCH
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
13
200K
200K
13
13
15
15
6,11,12
6,11
AC CHARACTERISTICS
(0
°
C
≤
T
A
≤
70
°
C, V
CC
=5.0V
±
10%. See notes 1,2.)
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| KMM5362205C2WG | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:2M x 36 DRAM SIMM using 1Mx16 and 4M Quad CAS EDO, 1K Refresh |
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| KMM53632000BKG | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:32M x 36 DRAM SIMM Using 16Mx4 & 16Mx1, 4K Refresh, 5V |
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| KMM53632000CKG | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:32M x 36 DRAM SIMM Using 16Mx4 & 16Mx1, 4K Refresh, 5V |
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