參數(shù)資料
型號(hào)： K4F160412C-B
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 4M x 4Bit CMOS Dynamic RAM with Fast Page Mode
中文描述： 4米× 4位的CMOS動(dòng)態(tài)隨機(jī)存儲(chǔ)器的快速頁(yè)面模式
文件頁(yè)數(shù)： 8/20頁(yè)
文件大?。?/td> 225K
代理商： K4F160412C-B
K4F170411C, K4F160411C
K4F170412C, K4F160412C
CMOS DRAM
NOTES
An initial pause of 200us is required after power-up followed by any 8 RAS-only refresh or CAS-before-RAS refresh cycles
before proper device operation is achieved.
V
IH
(min) and V
IL
(max) are reference levels for measuring timing of input signals. Transition times are measured between
V
IH
(min) and V
IL
(max) and are assumed to be 5ns for all inputs.
Measured with a load equivalent to 2 TTL(5V)/1 TTL(3.3V) loads and 100pF.
Operation within the
t
RCD
(max) limit insures that
t
RAC
(max) can be met.
t
RCD
(max) is specified as a reference point only.
If
t
RCD
is greater than the specified
t
RCD
(max) limit, then access time is controlled exclusively by
t
CAC
.
Assumes that
t
RCD
≥
t
RCD
(max).
t
OFF
(min)and
t
OEZ
(max) define the time at which the output achieves the open circuit condition and are not referenced V
oh
or
V
ol
.
t
WCS
,
t
RWD
,
t
CWD
and
t
AWD
are non restrictive operating parameters. They are included in the data sheet as electrical charac-
teristics only. If
t
WCS
≥
t
WCS
(min), the cycle is an early write cycle and the data output will remain high impedance for the dura-
tion of the cycle. If
t
CWD
≥
t
CWD
(min),
t
RWD
≥
t
RWD
(min) and
t
AWD
≥
t
AWD
(min), then the cycle is a read-modify-write cycle and the
data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the condition
of the data out is indeterminate.
Either
t
RCH
or
t
RRH
must be satisfied for a read cycle.
These parameters are referenced to CAS falling edge in early write cycles and to W falling edge in read-modify-write cycles.
Operation within the
t
RAD
(max) limit insures that
t
RAC
(max) can be met.
t
RAD
(max) is specified as a reference point only.
If
t
RAD
is greater than the specified
t
RAD
(max) limit, then access time is controlled by
t
AA
.
These specifications are applied in the test mode.
In test mode read cycle, the value of
t
RAC
,
t
AA
,
t
CAC
is delayed by 2ns to 5ns for the specified values. These parameters
should be specified in test mode cycles by adding the above value to the specified value in this data sheet.
If
t
RASS
≥
100us, then RAS precharge time must use
t
RPS
instead of
t
RP
.
For RAS-only refresh and burst CAS-before-RAS refresh mode, 4096(4K)/2048(2K) cycles of burst refresh must be exe-
cuted within 64ms/32ms before and after self refresh, in order to meet refresh specification.
For distributed CAS-before-RAS with 15.6us interval CAS-before-RAS refresh should be executed with in 15.6us immedi-
ately before and after self refresh in order to meet refresh specification.
5.
6.
7.
8.
9.
10.
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12.
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14.
1.
2.
3.
4.
15.
相關(guān)PDF資料
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
K4F160412C-F 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:4M x 4Bit CMOS Dynamic RAM with Fast Page Mode
K4F160412D 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:4M x 4Bit CMOS Dynamic RAM with Fast Page Mode
K4F160811D 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:2M x 8Bit CMOS Dynamic RAM with Fast Page Mode
K4F160812D 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:2M x 8Bit CMOS Dynamic RAM with Fast Page Mode
K4F170111C-BC60 制造商:Samsung Semiconductor 功能描述:
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