參數(shù)資料
型號(hào)： K4E641612D
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： CMOS DRAM
中文描述： 的CMOS內(nèi)存
文件頁數(shù)： 8/36頁
文件大?。?/td> 397K
代理商： K4E641612D
CMOS DRAM
K4E661612D,K4E641612D
Industrial Temperature
NOTES
An initial pause of 200us is required after power-up followed by any 8 R A S -only or C A S -before-R A S refresh cycles before
p r o p e r d e v i c e o p e r a t i o n i s a c h i e v e d .
Input voltage levels are Vih/Vil. V
IH
( m i n ) a n d V
IL
(max) are reference levels for measuring timing of input signals. Transition
t i m e s a r e m e a s u r e d b e t w e e n V
IH
(min) and V
IL
( m a x ) a n d a r e a s s u m e d t o b e 2 n s f o r a l l i n p u t s .
M e a s u r e d w i t h a l o a d e q u i v a l e n t t o 1 T T L l o a d a n d 1 0 0 p F .
O p e r a t i o n w i t h i n t h e
t
RCD
(max) limit insures that
t
RAC
( m a x ) c a n b e m e t .
t
RCD
(max) is specified as a reference point only.
If
t
RCD
is greater than the specified
t
RCD
(max) limit, then access time is controlled exclusively by
t
CAC
.
A s s u m e s t h a t
t
R C D
≥
t
R C D
( m a x ) .
This parameter defines the time at which the output achieves the open circuit condition and is not referenced to V
oh
or V
ol
.
t
W C S
,
t
RWD
,
t
C W D
a n d
t
A W D
are non restrictive operating parameters. They are included in the data sheet as electric charac-
teristics only. If
t
W C S
≥
t
W C S
(min), the cycles is an early write cycle and the data output will remain high impedance for the
duration of the cycle. If
t
C W D
≥
t
C W D
(min),
t
R W D
≥
t
R W D
( m i n ) a n d
t
AWD
≥
t
A W D
(min), then the cycle is a read-modify-write cycle
and the data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the
condition of the data out is indeterminate.
Either
t
R C H
or
t
R R H
m u s t b e s a t i s f i e d f o r a r e a d c y c l e .
T h i s p a r a m e t e r s a r e r e f e r e n c e d t o t h e C A S leading edge in early write cycles and to the W falling edge in O E controlled write
cycle and read-modify-write cycles.
Operation within the
t
R A D
(max) limit insures that
t
RAC
( m a x ) c a n b e m e t .
t
R A D
(max) is specified as a reference point only. If
t
RAD
is greater than the specified
t
R A D
(max) limit, then access time is controlled by
t
AA
.
T h e s e s p e c i f i e c a t i o n s a r e a p p l i e d i n t h e t e s t m o d e .
In test mode read cycle, the value of
t
R A C
,
t
AA
,
t
CAC
i s d e l a y e d b y 2 n s t o 5 n s f o r t h e s p e c i f i e d v a l u e s . T h e s e p a r a m e t e r s
should be specified in test mode cycles by adding the above value to the specified value in this data sheet.
t
ASC
,
t
CAH
are referenced to the earlier C A S falling edge.
t
CP
is specified from the last C A S rising edge in the previous cycle to the first C A S falling edge in the next cycle.
t
C W D
is referenced to the later C A S falling edge at word read-modify-write cycle.
K4E64(6)1612D Truth Table
R A S
L C A S
UCAS
W
O E
DQ0 - DQ7
DQ8-DQ15
STATE
H
X
X
X
X
Hi-Z
Hi-Z
S t a n d b y
L
H
H
X
X
Hi-Z
Hi-Z
R e f r e s h
L
L
H
H
L
D Q - O U T
Hi-Z
B y t e R e a d
L
H
L
H
L
Hi-Z
D Q - O U T
B y t e R e a d
L
L
L
H
L
D Q - O U T
D Q - O U T
W o r d R e a d
L
L
H
L
H
D Q - I N
-
Byte Write
L
H
L
L
H
-
D Q - I N
Byte Write
L
L
L
L
H
D Q - I N
D Q - I N
W o r d W r i t e
L
L
L
H
H
Hi-Z
Hi-Z
-
7 .
6 .
5 .
1 0 .
9 .
8 .
1 3 .
1 2 .
1 1 .
1 5 .
1 4 .
3 .
2 .
1 .
4 .
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