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參數資料
| 型號： | ISPLSI8840-90LB432 |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | In-System Programmable SuperBIG⑩ High Density PLD |
| 中文描述： | EE PLD, 16 ns, PBGA432 |
| 封裝： | BGA-432 |
| 文件頁數： | 19/23頁 |
| 文件大?。?/td> | 304K |
| 代理商： | ISPLSI8840-90LB432 |
Specifications
ispLSI 8840
19
CLK0, CLK1,
CLK2
CLKEN
Dedicated clock input for the GLB registers only. These clock inputs are connected to one of the clock
inputs of all GLB registers in the device.
Dedicated clock enable input for the GLB registers only. This input is available as a clock enable for
each GLB register in the device. Use of the clock enable input eliminates the need for the user to gate
the clock to the register.
Dedicated clock inputs for the I/O registers only. These clock inputs are connected to one of the clock
inputs of all I/O registers in the device.
Ground (GND)
Global Output Enable inputs.
Dedicated reset/preset pin connected to ALL registers in the device, GLB registers and
I/O registers. Each register can independently choose to be reset or preset when this signal goes
active. The active polarity is user-selectable.
Dedicated clock enable input for the I/O registers only. This input is available as a clock enable input for
all I/O registers in the device. Use of the clock enable input eliminates the need for the user to tie the
clock to the I/O register.
Input/Output
–
These are the general purpose I/O used by the logic array.
Input
–
Dedicated in-system programming enable input. When this is high, the BSCAN TAP
controller signals TMS, TDI, TDO and TCK are enabled. When this is brought low, the ISP State
Machine control signals MODE, SDI, SDO and SLCK are enabled. High-to-low transition will put the
device in the Lattice ISP programming mode and put all I/O in the high-Z state.
Input
–
This signal performs two functions. It is the Test Mode Select input signal when
ispEN
is logic
high. When
ispEN
is logic low, it controls the operation of the ISP State Machine.
No connect.
Dedicated clock inputs for the I/O registers only. These clock inputs are connected to the I/O registers
on the same side of the device only, they are not connected to all of the I/O registers. Use of these
quadrant I/O clocks gives the fastest tco from the device.
GIOCLK0,
GIOCLK1
GND
GOE
SET/RESET
IOCLKEN
I/O
BSCAN/
ispEN
TMS/MODE
NC
1
QIOCLK0
QIOCLK1
QIOCLK2
QIOCLK3
TCK/SCLK
Input
–
This signal performs two functions. It is the Test Clock input signal when
ispEN
is logic high.
When
ispEN
is logic low, it functions as a clock signal for the Serial Shift Register.
Input
–
This signal performs two functions. It is the Test Data input signal when
ispEN
is logic high.
When
ispEN
is logic low, it functions as an input to load programming data into the device. SDI is also
used as one of the two control signals for the ISP State Machine.
Output
–
This signal performs two functions. When
ispEN
is logic low, it reads the ISP data. When
ispEN
is high, it functions as Test Data Out.
Test Output Enable pin
–
This pin tristates all I/O pins when a logic low is driven.
Vcc
Power supply for the output drivers. The internal logic of the device is connected to VCC which is
always 5V. The output drivers are connected to VCCIO which can be equal to VCC or 3.3V. This allows
the output drivers to be powered from 3.3V, for example, to interface directly with another 3.3V device.
TDI/SDI
TDO/SDO
TOE
VCC
VCCIO
Signal Descriptions
Signal Name Description
1. NC pins are not to be connected to any active signals, VCC or GND.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| ISPLSI-8840V-125LB272 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Lattice Semiconductor Corporation 功能描述: |
| ispLSI8840V-125LB272 | 功能描述:CPLD - 復雜可編程邏輯器件 USE ispMACH 5000MV RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ISPLSI8840V-125LB492 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| ISPLSI-8840V-60LB272 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Lattice Semiconductor Corporation 功能描述: |
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