tHD:DAT Input Data Hold Time From SCL rising edge crossing" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� ISL95311WIU10Z-TK
寤犲晢锛� Intersil
鏂囦欢闋佹暩(sh霉)锛� 7/11闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC POT DGTL 10K OHM 10-MSOP
鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� Digitally Controlled Potentiometers
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 1
绯诲垪锛� XDCP™
鎺ョ墖锛� 128
闆婚樆锛堟瓙濮嗭級锛� 10k
闆昏矾鏁�(sh霉)锛� 1
婧害绯绘暩(sh霉)锛� 妯�(bi膩o)婧�(zh菙n)鍊� ±45 ppm/°C
瀛樺劜(ch菙)鍣ㄩ鍨嬶細 闈炴槗澶�
鎺ュ彛锛� I²C锛堣ō(sh猫)鍌欎綅鍧€锛�
闆绘簮闆诲锛� 2.7 V ~ 5.5 V
宸ヤ綔婧害锛� -40°C ~ 85°C
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 10-TFSOP锛�10-MSOP锛�0.118"锛�3.00mm 瀵級
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 10-MSOP
鍖呰锛� 妯�(bi膩o)婧�(zh菙n)鍖呰
鐢�(ch菐n)鍝佺洰閷勯爜闈細 1237 (CN2011-ZH PDF)
鍏跺畠鍚嶇ū锛� ISL95311WIU10Z-TKDKR
5
FN8084.1
February 6, 2008
tHD:DAT
Input Data Hold Time
From SCL rising edge crossing 30% of VCC to
SDA entering the 30% to 70% of VCC window
0ns
tSU:STO
STOP Condition Set-up time
From SCL rising edge crossing 70% of VCC, to
SDA rising edge crossing 30% of VCC
600
ns
tHD:STO
STOP Condition Hold Time
From SDA rising edge to SCL falling edge. Both
crossing 70% of VCC
600
ns
tDH
Output Data Hold Time
From SCL falling edge crossing 30% of VCC,
until SDA enters the 30% to 70% of VCC window
0ns
tR
(Note 14)
SDA and SCL Rise Time
From 30% to 70% of VCC
20 +
0.1 * Cb
250
ns
tF
(Note 14)
SDA and SCL Fall Time
From 70% to 30% of VCC
20 +
0.1 * Cb
250
ns
Cb
(Note 14)
Capacitive Loading of SDA or SCL
Total on-chip and off-chip
10
400
pF
Rpu
(Note 14)
SDA and SCL Bus Pull-Up Resistor
Off-Chip
Maximum is determined by tR and tF,
For Cb = 400pF, max is about 2k
惟~2.5k惟.
For Cb = 40pF, max is about 15k
惟~20k惟.
1k
tWP
(Notes 13)
Non-Volatile Write Cycle Time
12
20
ms
tSU:A
A0, A1 Set-up Time
Before START condition
600
ns
tHD:A
A0, A1 Hold Time
After STOP condition
600
ns
NOTES:
1. Typical values are for TA = +25掳C and 3.3V supply voltage.
2. LSB: [V(RW)127 鈥� V(RW)0]/127. V(RW)127 and V(RW)0 are V(RW) for the DCP register set to 7F hex and 00 hex respectively. LSB is the
incremental voltage when changing from one tap to an adjacent tap.
3. ZS error = V(RW)0/LSB.
4. FS error = [V(RW)127 鈥� V+]/LSB.
5. DNL = [V(RW)i 鈥� V(RW)i-1]/LSB-1, for i = 1 to 127. i is the DCP register setting.
6. INL = V(RW)i 鈥� (i LSB 鈥� V(RW)0) for i = 1 to 127.
7.
for i = 16 to 120 decimal, T = -40掳C to 85掳C. Max( ) is the maximum value of the wiper voltage and Min ( ) is the minimum value of the wiper
voltage over the temperature range.
8. MI =
|R127 鈥� R0|/127. R127 and R0 are the measured resistances for the DCP register set to 7F hex and 00 hex respectively.
9. Roffset = R0/MI, when measuring between RW and RL.
Roffset = R127/MI, when measuring between RW and RH.
10. RDNL = (Ri 鈥� Ri-1)/MI, for i = 16 to 127.
11. RINL = [Ri 鈥� (MI i) 鈥� R0]/MI, for i = 16 to 127.
12.
for i = 16 to 127, T = -40掳C to +85掳C. Max( ) is the maximum value of the resistance and Min ( ) is the minimum value of the resistance over the
temperature range.
13. tWP is the minimum cycle time to be allowed for any non-volatile Write by the user, unless Acknowledge Polling is used. It is the time from a valid
STOP condition at the end of a Write sequence of a I2C serial interface Write operation, to the end of the self-timed internal non-volatile write
cycle.
14. Recommended operating limits and are not production tested.
15. Parts are 100% tested at +85掳C. Over temperature limits established by characterization and are not production tested.
Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 15)
TYP
(Note 1)
MAX
(Note 15)
UNIT
TC
V
Max V RW
()
i
() Min V RW
()
i
()
鈥�
Max V RW
()
i
() Min V RW
()
i
()
+
[] 2
----------------------------------------------------------------------------------------------
106
125掳C
-----------------
=
TC
R
Max Ri
() Min Ri
()
鈥�
[]
Max Ri
() Min Ri
()
+
[] 2
----------------------------------------------------------------
10
6
125掳C
-----------------
=
ISL95311
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