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  • 參數(shù)資料
    型號: ISL9003AIEFZ-T
    廠商: INTERSIL CORP
    元件分類: 基準(zhǔn)電壓源/電流源
    英文描述: Low Noise LDO with Low IQ, High PSRR
    中文描述: 2.5 V FIXED POSITIVE LDO REGULATOR, 0.4 V DROPOUT, PDSO5
    封裝: ROHS COMPLIANT, PLASTIC, EIAJ, MO-203AA, SC-70, 5 PIN
    文件頁數(shù): 8/11頁
    文件大?。?/td> 210K
    代理商: ISL9003AIEFZ-T
    8
    FN6299.1
    December 21, 2006
    Block Diagram
    Functional Description
    The ISL9003A contains all circuitry required to implement a
    high performance LDO. High performance is achieved
    through a circuit that delivers fast transient response to
    varying load conditions. In a quiescent condition, the
    ISL9003A adjusts its biasing to achieve the lowest standby
    current consumption.
    The device also integrates current limit protection, smart
    thermal shutdown protection, and soft-start. Smart Thermal
    shutdown protects the device against overheating. Soft-start
    minimizes start-up input current surges without causing
    excessive device turn-on time.
    Power Control
    The ISL9003A has an enable pin, EN, to control power to the
    LDO output. When EN is low, the device is in shutdown
    mode. In this condition, all on-chip circuits are off, and the
    device draws minimum current, typically less than 0.3
    μ
    A.
    When the EN pin goes high, the device first polls the output
    of the UVLO detector to ensure that VIN voltage is at least
    2.1V (typical). Once verified, the device initiates a start-up
    sequence. During the start-up sequence, trim settings are
    first read and latched. Then, sequentially, the bandgap,
    reference voltage and current generation circuitry turn on.
    Once the references are stable, the LDO powers up.
    During operation, whenever the VIN voltage drops below
    about 1.84V, the ISL9003A immediately disables the LDO
    output. When VIN rises back above 2.1V (assuming the EN
    pin is high), the device re-initiates its start-up sequence and
    LDO operation resumes automatically.
    Reference Generation
    The reference generation circuitry includes a trimmed
    bandgap, a trimmed voltage reference divider, a trimmed
    current reference generator, and an RC noise filter. The filter
    includes the external capacitor connected to the CBYP pin.
    A 0.01
    μ
    F capacitor connected CBYP implements a 100Hz
    lowpass filter, and is recommended for most high
    performance applications. For the lowest noise application, a
    0.1
    μ
    F or greater CBYP capacitor should be used. This filters
    the reference noise to below the 10Hz – 1kHz frequency
    band, which is crucial in many noise-sensitive applications.
    The bandgap generates a zero temperature coefficient (TC)
    voltage for the regulator reference and other voltage
    references required for current generation and over-
    temperature detection.
    A current generator provides references required for
    adaptive biasing as well as references for LDO output
    current limit and thermal shutdown determination.
    LDO Regulation and Programmable Output Divider
    The LDO Regulator is implemented with a high-gain
    operational amplifier driving a PMOS pass transistor. The
    design of the ISL9003A provides a regulator that has low
    quiescent current, fast transient response, and overall
    stability across all operating and load current conditions.
    LDO stability is guaranteed for a 1
    μ
    F to 4.7
    μ
    F output
    capacitor that has a tolerance better than 20% and ESR less
    than 200m
    Ω
    . The design is performance-optimized for a 1
    μ
    F
    capacitor. Unless limited by the application, use of an output
    capacitor value above 4.7
    μ
    F is not recommended as LDO
    performance improvement is minimal.
    VO
    GND
    BANDGAP AND
    TEMPERATURE
    SENSOR
    UVLO
    VIN
    SD
    CONTROL
    LOGIC
    VOLTAGE AND
    REFERENCE
    GENERATOR
    CBYP
    1.0V
    0.94V
    0.9V
    GND
    SHORT CIRCUIT,
    THERMAL PROTECTION,
    SOFT-START
    +
    -
    ISL9003A
    相關(guān)PDF資料
    PDF描述
    ISL9003AIEHZ-T Low Noise LDO with Low IQ, High PSRR
    ISL9003AIEJZ-T Low Noise LDO with Low IQ, High PSRR
    ISL9003AIEKZ-T Low Noise LDO with Low IQ, High PSRR
    ISL9003AIEMZ-T Low Noise LDO with Low IQ, High PSRR
    ISL9003AIENZ-T Low Noise LDO with Low IQ, High PSRR
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