6 FN6578.1 July 14, 2010 Input High Current, ISEL2H,
參數(shù)資料
型號(hào): ISL54406IRTZ-T
廠商: Intersil
文件頁(yè)數(shù): 13/16頁(yè)
文件大小: 0K
描述: IC SWITCH DUAL SPST 10-TDFN
標(biāo)準(zhǔn)包裝: 1
功能: 開關(guān)
電路: 2 x SPST - NO
導(dǎo)通狀態(tài)電阻: 2.8 歐姆
電壓電源: 單電源
電壓 - 電源,單路/雙路(±): 2.7 V ~ 5 V
電流 - 電源: 7µA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 10-VFDFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 10-TDFN/MLP(3x3)
包裝: 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁(yè)面: 1247 (CN2011-ZH PDF)
其它名稱: ISL54406IRTZ-TDKR
ISL54406
6
FN6578.1
July 14, 2010
Input High Current, ISEL2H,
ISEL1H
VDD = 3.6V, VSEL2 = 3.6V, VSEL1 = 3.6V
Full
-2
1
2
A
SEL1 Pull-Down Resistor,
RSEL1
VDD = 3.6V, VSEL2 = 3.6V, VSEL1 = 0V
Full
-
4
-
SEL2 Pull-Down Resistor,
RSEL2
VDD = 3.6V, VSEL2 = 0V, VSEL1 = 3.6V
Full
-
4
-
NOTES:
11. VSELx = Input voltage to perform proper function.
12. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this
data sheet.
13. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established
by characterization and are not production tested.
14. Flatness is defined as the difference between maximum and minimum value of ON-resistance over the specified analog signal
range.
15. rON matching between channels is calculated by subtracting the channel with the highest max rON value from the channel
with lowest max rON value.
16. Limits established by characterization and are not production tested.
17. Click and Pop Reduction specifications are limited by test equipment.
Test Circuits and Waveforms
FIGURE 1A. MEASUREMENT POINTS
Repeat test for all switches. CL includes fixture and stray
capacitance.
FIGURE 1B. TEST CIRCUIT
FIGURE 1. SWITCHING TIMES
Electrical Specifications - 2.7V to 3.6V Supply Test Conditions: VDD = +3.0V, GND = 0V, VSELx_H = 1.4V,
VSELx_L= 0.5V, (Notes 11), Unless Otherwise Specified (Continued)
Boldface limits apply over the operating temperature range,
-40°C to +85°C. (Continued)
PARAMETER
TEST CONDITIONS
TEMP
(°C)
MIN
(Notes 12, 13) TYP
MAX
(Notes 12, 13) UNITS
50%
tr < 20ns
tf < 20ns
tOFF
90%
VSEL2H
0V
VINPUT
VSEL2L
tON
LOGIC
INPUT
SWITCH
INPUT
SWITCH
OUTPUT
90%
VOUT
VOUT
V(INPUT)
RL
RL rON
+
------------------------
=
SWITCH
INPUT
VSEL2
VLOUT/ROUT
RL
CL
OUT
IN
50
Ω
10pF
VDD
SEL1
VLIN/RIN
0.1F
GND
SEL2
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