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參數(shù)資料
| 型號： | XC6VLX240T-2FFG1156C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 11/11頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA VIRTEX 6 241K 1156FFGBGA |
| 產(chǎn)品培訓模塊： | Virtex-6 FPGA Overview |
| 產(chǎn)品變化通告： | Virtex-6 FIFO Input Logic Reset 18/Apr/2011 |
| 標準包裝： | 1 |
| 系列： | Virtex® 6 LXT |
| LAB/CLB數(shù)： | 18840 |
| 邏輯元件/單元數(shù)： | 241152 |
| RAM 位總計： | 15335424 |
| 輸入/輸出數(shù)： | 600 |
| 電源電壓： | 0.95 V ~ 1.05 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 1156-BBGA，F(xiàn)CBGA |
| 供應商設(shè)備封裝： | 1156-FCBGA（35x35） |
| 其它名稱： | 122-1685 |
Virtex-6 Family Overview
DS150 (v2.4) January 19, 2012
Product Specification
9
This block is highly configurable to system design requirements and can operate 1, 2, 4, or 8 lanes at the 2.5 Gb/s data rate
and the 5.0 Gb/s data rate. For high-performance applications, advanced buffering techniques of the block offer a flexible
maximum payload size of up to 1024 bytes. The integrated block interfaces to the GTX transceivers for serial connectivity,
and to block RAMs for data buffering. Combined, these elements implement the Physical Layer, Data Link Layer, and
Transaction Layer of the PCI Express protocol.
Xilinx provides a light-weight, configurable, easy-to-use LogiCORE wrapper that ties the various building blocks (the
integrated block for PCI Express, the GTX transceivers, block RAM, and clocking resources) into an Endpoint or Root Port
solution. The system designer has control over many configurable parameters: lane width, maximum payload size, FPGA
logic interface speeds, reference clock frequency, and base address register decoding and filtering.
More information and documentation on solutions for PCI Express designs can be found at:
10/100/1000 Mb/s Ethernet Controller (2,500 Mb/s Supported)
An integrated Tri-mode Ethernet MAC (TEMAC) block is easily connected to the FPGA logic, the GTX transceivers, and the
SelectIO resources. This TEMAC block saves logic resources and design effort. All of the Virtex-6 devices (except the
XC6VLX760) have four TEMAC blocks, implementing the link layer of the OSI protocol stack. The CORE Generator
software GUI helps to configure flexible interfaces to GTX transceiver or SelectIO technology, to the FPGA logic, and to a
microprocessor (when required). The TEMAC is designed to the IEEE Std 802.3-2005 specification. 2,500 Mb/s support is
also available.
Virtex-6 FPGA Ordering Information
Table 4 shows the speed and temperature grades available in the different Virtex-6 devices. Some devices might not be
available in every speed and temperature grade.
The Virtex-6 FPGA ordering information shown in Figure 1 applies to all packages including Pb-Free.
Table 4: Virtex-6 FPGAs Speed Grade and Temperature Ranges
Device Family
Speed Grade and Temperature Range
Commercial (C)
0°C to +85°C
Extended (E)
0°C to +100°C
Industrial (I)
-40°C to +100°C
Virtex-6 LXT
-3, -2, -1, -1L
-2
-2, -1, -1L
Virtex-6 SXT
-3, -2, -1, -1L
-2
-2, -1, -1L
Virtex-6 HXT
-3, -2, -1
-2
-2, -1
X-Ref Target - Figure 1
Figure 1: Virtex-6 FPGA Ordering Information
Example: XC6VLX240T-1FFG1156C
Device Type
Temperature Range:
Number of Pins(3)
Package Type
Speed Grade
(-1, -L1(1), -2, -3(2))
Pb-Free
DS150_01_103111
Note:
1) -L1 is the ordering code for the lower power -1L speed grade.
-L1 is not available in the Virtex-6 HXT devices. See
the Virtex-6 FPGA data sheet for more information.
2) -3 speed grades are not available in all devices.
3) Some package names do not exactly match the number
of pins present on that package. Please see UG365: Virtex-6 FPGA Packaging and Pinout Specifications for package details.
I = Industrial (Tj = –40°C to +100°C)
E = Extended (Tj = 0°C to +100°C)
C = Commercial (Tj = 0°C to +85°C)
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