參數(shù)資料
型號(hào)： IDT74FCT824CLB
廠商： Integrated Device Technology, Inc.
英文描述： HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
中文描述： 高性能CMOS總線接口寄存器
文件頁(yè)數(shù)： 6/8頁(yè)
文件大?。?/td> 186K
代理商： IDT74FCT824CLB
7.19
6
IDT54/74FCT821/823/824/825A/B/C
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter is guaranteed but not tested.
2608 tbl* 08
IDT54/74FCT821A/
823A/824A/825A
Com'l.
IDT54/74FCT821B/
823B/824B/825B
Com'l.
IDT54/74FCT821C/
823C/824C/825C
Com'l.
Test
Mil.
Mil.
Mil.
Parameter
t
PLH
t
PHL
Description
Conditions
(1)
C
L
= 50pF
R
L
= 500
C
L
= 300pF
(3)
R
L
= 500
C
L
= 50pF
R
L
= 500
Min.
(2)
Max.
Min.
(2)
Max.
Min.
(2)
Max.
Min.
(2)
Max.
Min.
(2)
Max.
Min.
(2)
Max.
Unit
Propagation Delay
CP to Y
I
(
OE
= LOW)
—
10.0
—
11.5
—
7.5
—
8.5
—
6.0
—
7.0
ns
—
20.0
—
20.0
—
15.0
—
16.0
—
12.5
—
13.5
t
SU
Set-up Time HIGH or LOW
D
i
to CP
Hold Time HIGH or LOW
D
I
to CP
Set-up Time HIGH or LOW
EN
to CP
Hold Time HIGH or LOW
EN
to CP
Propagation Delay,
CLR
to
Y
I
4.0
—
4.0
—
3.0
—
3.0
—
3.0
—
3.0
—
ns
t
H
2.0
—
2.0
—
1.5
—
1.5
—
1.5
—
1.5
—
ns
t
SU
4.0
—
4.0
—
3.0
—
3.0
—
3.0
—
3.0
—
ns
t
H
2.0
—
2.0
—
0
—
0
—
0
—
0
—
ns
t
PHL
—
14.0
—
15.0
—
9.0
—
9.5
—
8.0
—
8.5
ns
t
REM
Recovery Time
CLR
to CP
6.0
—
7.0
—
6.0
—
6.0
—
6.0
—
6.0
—
ns
t
W
CP Pulse Width
HIGH or LOW
CLR
Pulse Width
LOW
Output Enable Time
OE
to Y
I
7.0
—
7.0
—
6.0
—
6.0
—
6.0
—
6.0
—
ns
t
W
6.0
—
7.0
—
6.0
—
6.0
—
6.0
—
6.0
—
ns
t
PZH
t
PZL
C
L
= 50pF
R
L
= 500
C
L
= 300pF
(3)
R
L
= 500
C
L
= 5pF
(3)
R
L
= 500
C
L
= 50pF
R
L
= 500
—
12.0
—
13.0
—
8.0
—
9.0
—
7.0
—
8.0
ns
—
23.0
—
25.0
—
15.0
—
16.0
—
12.5
—
13.5
t
PHZ
t
PLZ
Output Disable Time
OE
to Y
I
—
7.0
—
8.0
—
6.5
—
7.0
—
6.2
—
6.2
ns
—
8.0
—
9.0
—
7.5
—
8.0
—
6.5
—
6.5
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