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參數資料
| 型號： | IDT74ALVC162835APV |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | ALVC/VCX/A SERIES, 18-BIT DRIVER, TRUE OUTPUT, PDSO56 |
| 封裝： | 0.635 MM PITCH, SSOP-56 |
| 文件頁數： | 2/6頁 |
| 文件大?。?/td> | 104K |
| 代理商： | IDT74ALVC162835APV |
2
EXTENDED COMMERCIAL TEMPERATURE RANGE
IDT74ALVC162835A
3.3V CMOS 18-BIT UNIVERSAL BUS DRIVER W/ 3-STATE OUTPUTS
SSOP/
TSSOP/ TVSOP
TOP VIEW
FUNCTION TABLE(1)
NOTE:
1. As applicable to the device type.
ABSOLUTE MAXIMUM RATING (1)
Symbol
Description
Max.
Unit
VTERM(2)
Terminal Voltage
with Respect to GND
– 0.5 to + 4.6
V
VTERM(3)
Terminal Voltage
with Respect to GND
– 0.5 to
VCC + 0.5
V
TSTG
Storage Temperature
– 65 to + 150
°C
IOUT
DC Output Current
– 50 to + 50
mA
IIK
Continuous Clamp Current,
VI < 0 or VI
> VCC
± 50
mA
IOK
Continuous Clamp Current, VO < 0
– 50
mA
ICC
ISS
Continuous Current through
each VCC or GND
±100
mA
NEW16link
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
2. VCC terminals.
3. All terminals except VCC.
PIN DESCRIPTION
NOTES:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High-Impedance
↑ = LOW-to-HIGH Transition
2. Output level before indicated steady-state input conditions were estab-
lished, provided that CLK is HIGH before LE went LOW.
3. Output level before the indicated steady-state input conditions were es-
tablished.
GND
SO 56-1
SO 56-2
SO 56-3
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
48
49
50
51
52
53
54
55
56
1
GND
25
26
27
28
32
31
30
29
GND
NC
A1
NC
Y1
Y 2
Y3
Y4
Y5
Y 6
Y7
Y8
Y9
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
A 2
A3
A4
A 5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
VCC
A16
A17
A18
GND
VCC
CLK
GND
VCC
GND
OE
LE
PIN CONFIGURATION
CAPACITANCE (TA = +25oC, f = 1.0MHz)
Symbol
Parameter(1)
Conditions
Min.
Typ.
Max.
Unit
CIN
Input
Capacitance
VIN = 0V
4
5
6
pF
COUT
Output
Capacitance
VOUT = 0V
79
pF
CI/O
I/O Port
Capacitance
VIN = 0V
79
pF
Inputs
Output
OE
LE
CLK
Ax
Yx
HX
X
Z
LH
X
L
LH
X
H
LL
↑
LL
↑
HH
LL
H
X
Y
0
(2)
LL
L
X
Y
0
(3)
Pin Names
Description
OE
3-State Output Enable Inputs (Active LOW)
CLK
Register Input Clock
LE
Latch Enable (Transparent HIGH)
Ax
Data Inputs
Yx
3-State Outputs
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