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參數(shù)資料
| 型號(hào)： | IDT72V90823J |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 7/21頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DGTL SW 2048X2048 84-PLCC |
| 標(biāo)準(zhǔn)包裝： | 30 |
| 系列： | 72V |
| 類型： | 多路復(fù)用器 |
| 電路： | 1 x 16:16 |
| 獨(dú)立電路： | 1 |
| 電壓電源： | 單電源 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 84-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 84-PLCC（29.21x29.21） |
| 包裝： | 管件 |
| 其它名稱： | 72V90823J |
Technical Note
BU4015B,BU4015BF,BU4021B,BU4021BF,
BU4094BC,BU4094BCF,BU4094BCFV,BU4538B,BU4028B
15/17
www.rohm.com
2009.06 - Rev.A
2009 ROHM Co., Ltd. All rights reserved.
1
2
4
5
6
7
14
13
12
9
Q4
B
D
A
Q8
C
11
3
10
Q1
Q2
Q0
Q7
Q9
Q5
Q6
8
VSS
15
Q3
16
VDD
Q2
Q0
Q7
Q9
Q5
Q6
Q3
Q1
B
C
D
A
Q4
Q8
IN
●Description of BU4028B series model
Function: BCD to decimal decoder
1) Description of operation
BU4028B is a decoder to convert BCD signals into decimal signals. Out of 10 outputs of Q0~Q9, output applicable for the
input code of A~D becomes “H” level and all other outputs become “L” level. When the input of D is made to be inhibit input
by using 3 inputs of A~C, this product can be used as a 1-OF-8 decoder.
PIN arrangement
Block diagram
Truth table
Switching characteristics
●Notes for use
1. Absolute maximum ratings
An excess in the absolute maximum ratings, such as supply voltage, temperature range of operating conditions, etc., can break
down the devices, thus making impossible to identify breaking mode, such as a short circuit or an open circuit. If any over rated
values will expect to exceed the absolute maximum ratings, consider adding circuit protection devices, such as fuses.
2. Connecting the power supply connector backward
Connecting of the power supply in reverse polarity can damage IC. Take precautions when connecting the power supply
lines. An external direction diode can be added.
3. Power supply lines
Design PCB layout pattern to provide low impedance GND and supply lines. To obtain a low noise ground and supply line,
separate the ground section and supply lines of the digital and analog blocks. Furthermore, for all power supply terminals
to ICs, connect a capacitor between the power supply and the GND terminal. When applying electrolytic capacitors in the
circuit, not that capacitance characteristic values are reduced at low temperatures.
4. GND voltage
The potential of GND pin must be minimum potential in all operating conditions.
5. Thermal design
Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating conditions.
6. Inter-pin shorts and mounting errors
Use caution when positioning the IC for mounting on printed circuit boards. The IC may be damaged if there is any
connection error or if pins are shorted together.
7. Actions in strong electromagnetic field
Use caution when using the IC in the presence of a strong electromagnetic field as doing so may cause the IC to malfunction.
8. Testing on application boards
When testing the IC on an application board, connecting a capacitor to a pin with low impedance subjects the IC to stress.
Always discharge capacitors after each process or step. Always turn the IC's power supply off before connecting it to or
removing it from a jig or fixture during the inspection process. Ground the IC during assembly steps as an antistatic
measure. Use similar precaution when transporting or storing the IC.
9. Ground Wiring Pattern
When using both small signal and large current GND patterns, it is recommended to isolate the two ground patterns,
placing a single ground point at the ground potential of application so that the pattern wiring resistance and voltage
variations caused by large currents do not cause variations in the small signal ground voltage. Be careful not to change the
GND wiring pattern of any external components, either.
10. Unused input terminals
Connect all unused input terminals to VDD or VSS in order to prevent excessive current or oscillation
Insertion of a resistor (100k
approx.) is also recommended
PIN description
PIN
No.
Symb
ol
I/
O
Function
1
Q4
O
Output 4
2
Q2
O
Output 2
3
Q0
O
Output 0
4
Q7
O
Output 7
5
Q9
O
Output 9
6
Q5
O
Output 5
7
Q6
O
Output 6
8
VSS
―
Power supply(-)
9
Q8
O
Output 8
10
A
I
Input A
11
D
I
Input D
12
C
I
Input C
13
B
I
Input B
14
Q1
O
Output 1
15
Q3
O
Output 3
16
VDD
―
Power supply (+)
D
C
B
A
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
D
B
OUTPUT
INPUT
C
A
Q9 Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0
L
LLH
LL
L
LL
H
L
LL
H
L
LL
L
LL
L
H
L
LL
H
LL
L
LH
L
LH
L
LL
H
LL
L
LH
L
H
LL
L
HL
L
HHL
LL
LH
L
LL
L
HHH
LH
LL
L
LL
L
H
LLL
LL
HL
L
LL
L
H
LLH
HL
LL
L
LL
L
H
HL
H
L
LL
L
LL
L
HL
H
LL
L
LL
L
HH
L
LL
L
LL
L
HH
L
H
LL
L
LL
L
H
HHL
LL
L
LL
L
H
HHH
LL
L
LL
L
LLL
LL
L
LL
L
90%
50%
10%
90%
50%
10%
tTLH
tTHL
Input wave
Output wave
Neg.
Pos.
tPHL
tPLH
20[ns]
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