參數(shù)資料
型號： IDT71V3559SA80BQ
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： DRAM
英文描述： 128K x 36, 256K x 18, 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter, Flow-Through Outputs
中文描述： 256K X 18 ZBT SRAM, 8 ns, PBGA165
封裝： 13 X 15 MM, FBGA-165
文件頁數(shù)： 1/28頁
文件大?。?/td> 996K
代理商： IDT71V3559SA80BQ
OCTOBER 2004
DSC-5282/07
1
2004 Integrated Device Technology, Inc.
128K x 36, 256K x 18,
3.3V Synchronous ZBT SRAMs
3.3V I/O, Burst Counter,
Flow-Through Outputs
Pin Description Summary
it read or write.
The IDT71V3557/59 contain address, data-in and control signal
registers. The outputs are flow-through (no output data register). Output
enable is the only asynchronous signal and can be used to disable the
outputs at any given time.
A Clock Enable (
CEN
) pin allows operation of the IDT71V3557/59
to be suspended as long as necessary. All synchronous inputs are
ignored when (
CEN
) is high and the internal device registers will hold
their previous values.
There are three chip enable pins (
CE
1
, CE
2
,
CE
2
) that allow the user
to deselect the device when desired. If any one of these three is not asserted
when ADV/
LD
is low, no new memory operation can be
initiated. However, any pending data transfers (reads or writes) will
be completed. The data bus will tri-state one cycle after chip is de-
selected or a write is initiated.
The IDT71V3557/59 have an on-chip burst counter. In the burst
mode, the IDT71V3557/59 can provide four cycles of data for a single
address presented to the SRAM. The order of the burst sequence is
defined by the
LBO
input pin. The
LBO
pin selects between linear and
interleaved burst sequence. The ADV/
LD
signal is used to load a new
external address (ADV/
LD
= LOW) or increment the internal burst counter
(ADV/
LD
= HIGH).
The IDT71V3557/59 SRAMs utilize IDT's latest high-performance
CMOS process and are packaged in a JEDEC standard 14mmx 20mm
100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array
(BGA) and a 165 fine pitch ball grid array (fBGA).
Features
N
128K x 36, 256K x 18 memory configurations
N
Supports high performance system speed - 100 MHz
(7.5 ns Clock-to-Data Access)
N
ZBT
TM
Feature - No dead cycles between write and read
cycles
N
Internally synchronized output buffer enable eliminates
the need to control
OE
N
Single R/
W
(READ/WRITE) control pin
N
4-word burst capability (Interleaved or linear)
N
Individual byte write (
BW
1
-
N
Three chip enables for simple depth expansion
N
3.3V power supply (±5%), 3.3V (±5%) I/O Supply (V
DDQ
)
N
Optional Boundary Scan JTAG Interface (IEEE 1149.1
complaint)
N
Packaged in a JEDEC Standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine
pitch ball grid array (fBGA)
Description
The IDT71V3557/59 are 3.3V high-speed 4,718,592-bit (4.5 Mega-
bit) synchronous SRAMs organized as 128K x 36/256K x 18. They are
designed to elimnate dead bus cycles when turning the bus around
between reads and writes, or writes and reads. Thus they have been
given the name ZBT
TM
, or Zero Bus Turnaround.
Address and control signals are applied to the SRAMduring one clock
cycle, and on the next clock cycle the associated data cycle occurs, be
BW
4
) control (May tie active)
A
0
-A
17
Address Inputs
Input
Synchronous
CE
1
, CE
2
,
CE
2
Chip Enables
Input
Synchronous
OE
Output Enable
Input
Asynchronous
R/
W
Read/Write Signal
Input
Synchronous
CEN
Clock Enable
Input
Synchronous
BW
1
,
BW
2
,
BW
3
,
BW
4
Individual Byte Write Selects
Input
Synchronous
CLK
Clock
Input
N/A
ADV/
LD
Advance burst address / Load new address
Input
Synchronous
LBO
Linear / Interleaved Burst Order
Input
Static
TMS
Test Mode Select
Input
Synchronous
TDI
Test Data Input
Input
Synchronous
TCK
Test Clock
Input
N/A
TDO
Test Data Output
Output
Synchronous
TRST
JTAG Reset (Optional)
Input
Asynchronous
ZZ
Sleep Mode
Input
Synchronous
I/O
0
-I/O
31
, I/O
P1
-I/O
P4
Data Input / Output
I/O
Synchronous
V
DD
, V
DDQ
Core Power I/O Power
Supply
Static
V
SS
Ground
Supply
Static
5282 tbl 01
IDT71V3557S
IDT71V3559S
IDT71V3557SA
IDT71V3559SA
相關(guān)PDF資料
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IDT71V3559SA80PFI RAC5-SB(-E)(-ST) Series - Powerline Regulated AC-DC Converters; Output Voltage (Vdc): 24V; Features: Very Compact AC-DC Power Supply; 5 Watt PCB Mount Package; Universal Input Voltage Range; 3000VAC Isolation; Low Output Ripple and Noise; Short Circuit Protected; UL Certified
IDT71V3557S85BQ Ceramic Conformally Coated / Radial 'Standard & High Voltage Golden Max'; Capacitance [nom]: 0.068uF; Working Voltage (Vdc)[max]: 200V; Capacitance Tolerance: +/-10%; Dielectric: Multilayer Ceramic, Conformally Coated; Temperature Coefficient: X7R; Lead Style: Radial Leaded; Lead Dimensions: 0.200" Lead Spacing; Body Dimensions: 0.300" x 0.390" x 0.200"; Container: Bag; Qty per Container: 250
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參數(shù)描述
IDT71V3559SA80BQ8 功能描述:IC SRAM 4MBIT 80NS 165FBGA RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:576 系列:- 格式 - 存儲器:閃存 存儲器類型:閃存 - NAND 存儲容量:512M（64M x 8） 速度:- 接口:并聯(lián) 電源電壓:2.7 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應(yīng)商設(shè)備封裝:48-TSOP 包裝:托盤 其它名稱:497-5040
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IDT71V3559SA80BQG8 功能描述:IC SRAM 4MBIT 80NS 165FBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:576 系列:- 格式 - 存儲器:閃存 存儲器類型:閃存 - NAND 存儲容量:512M（64M x 8） 速度:- 接口:并聯(lián) 電源電壓:2.7 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應(yīng)商設(shè)備封裝:48-TSOP 包裝:托盤 其它名稱:497-5040
IDT71V3559SA80BQGI 功能描述:IC SRAM 4MBIT 80NS 165FBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:576 系列:- 格式 - 存儲器:閃存 存儲器類型:閃存 - NAND 存儲容量:512M（64M x 8） 速度:- 接口:并聯(lián) 電源電壓:2.7 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應(yīng)商設(shè)備封裝:48-TSOP 包裝:托盤 其它名稱:497-5040
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