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參數(shù)資料
| 型號(hào)： | IDT7143SA90PFB |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | HIGH-SPEED 2K x 16 CMOS DUAL-PORT STATIC RAMS |
| 中文描述： | 2K X 16 DUAL-PORT SRAM, 90 ns, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁數(shù)： | 1/16頁 |
| 文件大?。?/td> | 140K |
| 代理商： | IDT7143SA90PFB |
2000 Integrated Device Technology, Inc.
DSC 2746/11
1
HIGH SPEED
2K X 16 DUAL-PORT
SRAM
IDT7133SA/LA
IDT7143SA/LA
N
High-speed access
–
Mlitary: 25/35/45/55/70/90ns (max.)
–
Industrial: 25/35/55ns (max.)
–
Commercial: 20/25/35/45/55/70/90ns (max.)
N
Low-power operation
–
IDT7133/43SA
Active: 1150mW (typ.)
Standby: 5mW (typ.)
–
IDT7133/43LA
Active: 1050mW (typ.)
Standby: 1mW (typ.)
N
Versatile control for write: separate write control for lower
and upper byte of each port
N
MASTER IDT7133 easily expands data bus width to 32 bits
or more using SLAVE IDT7143
N
On-chip port arbitration logic (IDT7133 only)
NOTE:
1.
IDT7133 (MASTER):
BUSY
is open drain output and requires pull-up resistor.
IDT7143 (SLAVE):
BUSY
is input.
N
BUSY
output flag on IDT7133;
BUSY
input on IDT7143
N
Fully asynchronous operation from either port
N
Battery backup operation–2V data retention
N
TTL-compatible; single 5V (±10%) power supply
N
Available in 68-pin ceramic PGA, Flatpack, PLCC and 100-
pin TQFP
N
Mlitary product compliant to MIL-PRF-38535 QML
N
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
The IDT7133/7143 are high-speed 2K x 16 Dual-Port Static RAMs.
The IDT7133 is designed to be used as a stand-alone 16-bit Dual-Port
RAMor as a “MASTER” Dual-Port RAMtogether with the IDT7143
“SLAVE” Dual-Port in 32-bit-or-more word width systems. Using the
IDT MASTER/SLAVE Dual-Port RAMapproach in 32-bit-or-wider
I/O
CONTROL
MEMORY
ARRAY
ARBITRATION
LOGIC
(IDT7133 ONLY)
R/
W
LUB
CE
L
R/
W
LLB
OE
L
I/O
0L
- I/O
7L
BUSY
L
A
0L
CE
L
R/
W
RUB
CE
R
R/
W
RLB
OE
R
I/O
8R
- I/O
15R
I/O
0R
- I/O
7R
BUSY
R
(1)
A
0R
CE
R
2746 drw 01
A
10L
ADDRESS
DECODER
A
10R
I/O
CONTROL
ADDRESS
DECODER
11
11
(1)
I/O
8L
- I/O
15L
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